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@@ -548,9 +548,16 @@ static int
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gf100_fifo_oneinit(struct nvkm_fifo *base)
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{
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struct gf100_fifo *fifo = gf100_fifo(base);
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- struct nvkm_device *device = fifo->base.engine.subdev.device;
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+ struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
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+ struct nvkm_device *device = subdev->device;
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int ret;
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+ /* Determine number of PBDMAs by checking valid enable bits. */
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+ nvkm_wr32(device, 0x002204, 0xffffffff);
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+ fifo->pbdma_nr = hweight32(nvkm_rd32(device, 0x002204));
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+ nvkm_debug(subdev, "%d PBDMA(s)\n", fifo->pbdma_nr);
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+
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+
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ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x1000,
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false, &fifo->runlist.mem[0]);
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if (ret)
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@@ -587,18 +594,15 @@ static void
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gf100_fifo_init(struct nvkm_fifo *base)
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{
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struct gf100_fifo *fifo = gf100_fifo(base);
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- struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
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- struct nvkm_device *device = subdev->device;
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+ struct nvkm_device *device = fifo->base.engine.subdev.device;
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int i;
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- nvkm_wr32(device, 0x000204, 0xffffffff);
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- nvkm_wr32(device, 0x002204, 0xffffffff);
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-
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- fifo->spoon_nr = hweight32(nvkm_rd32(device, 0x002204));
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- nvkm_debug(subdev, "%d PBDMA unit(s)\n", fifo->spoon_nr);
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+ /* Enable PBDMAs. */
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+ nvkm_wr32(device, 0x000204, (1 << fifo->pbdma_nr) - 1);
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+ nvkm_wr32(device, 0x002204, (1 << fifo->pbdma_nr) - 1);
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- /* assign engines to PBDMAs */
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- if (fifo->spoon_nr >= 3) {
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+ /* Assign engines to PBDMAs. */
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+ if (fifo->pbdma_nr >= 3) {
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nvkm_wr32(device, 0x002208, ~(1 << 0)); /* PGRAPH */
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nvkm_wr32(device, 0x00220c, ~(1 << 1)); /* PVP */
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nvkm_wr32(device, 0x002210, ~(1 << 1)); /* PMSPP */
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@@ -608,7 +612,7 @@ gf100_fifo_init(struct nvkm_fifo *base)
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}
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/* PBDMA[n] */
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- for (i = 0; i < fifo->spoon_nr; i++) {
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+ for (i = 0; i < fifo->pbdma_nr; i++) {
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nvkm_mask(device, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000);
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nvkm_wr32(device, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */
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nvkm_wr32(device, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */
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