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@@ -308,9 +308,7 @@ vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
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for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
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u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
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PANEL_PORT_SELECT_MASK;
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- if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
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- return pipe;
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- if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
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+ if (port_sel == PANEL_PORT_SELECT_VLV(port))
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return pipe;
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}
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@@ -4327,6 +4325,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
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u32 pp_on, pp_off, pp_div, port_sel = 0;
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int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
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int pp_on_reg, pp_off_reg, pp_div_reg;
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+ enum port port = dp_to_dig_port(intel_dp)->port;
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if (HAS_PCH_SPLIT(dev)) {
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pp_on_reg = PCH_PP_ON_DELAYS;
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@@ -4361,12 +4360,9 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
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/* Haswell doesn't have any port selection bits for the panel
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* power sequencer any more. */
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if (IS_VALLEYVIEW(dev)) {
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- if (dp_to_dig_port(intel_dp)->port == PORT_B)
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- port_sel = PANEL_PORT_SELECT_DPB_VLV;
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- else
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- port_sel = PANEL_PORT_SELECT_DPC_VLV;
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+ port_sel = PANEL_PORT_SELECT_VLV(port);
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} else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
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- if (dp_to_dig_port(intel_dp)->port == PORT_A)
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+ if (port == PORT_A)
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port_sel = PANEL_PORT_SELECT_DPA;
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else
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port_sel = PANEL_PORT_SELECT_DPD;
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