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@@ -1,231 +0,0 @@
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-/*
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- * r7a72100 clock framework support
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- *
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- * Copyright (C) 2013 Renesas Solutions Corp.
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- * Copyright (C) 2012 Phil Edworthy
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- * Copyright (C) 2011 Magnus Damm
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License as published by
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- * the Free Software Foundation; version 2 of the License.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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- * GNU General Public License for more details.
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- */
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-#include <linux/init.h>
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-#include <linux/kernel.h>
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-#include <linux/io.h>
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-#include <linux/sh_clk.h>
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-#include <linux/clkdev.h>
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-
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-#include "common.h"
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-#include "r7s72100.h"
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-
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-/* Frequency Control Registers */
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-#define FRQCR 0xfcfe0010
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-#define FRQCR2 0xfcfe0014
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-/* Standby Control Registers */
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-#define STBCR3 0xfcfe0420
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-#define STBCR4 0xfcfe0424
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-#define STBCR7 0xfcfe0430
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-#define STBCR9 0xfcfe0438
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-#define STBCR10 0xfcfe043c
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-
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-#define PLL_RATE 30
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-
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-static struct clk_mapping cpg_mapping = {
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- .phys = 0xfcfe0000,
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- .len = 0x1000,
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-};
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-
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-/* Fixed 32 KHz root clock for RTC */
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-static struct clk r_clk = {
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- .rate = 32768,
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-};
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-
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-/*
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- * Default rate for the root input clock, reset this with clk_set_rate()
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- * from the platform code.
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- */
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-static struct clk extal_clk = {
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- .rate = 13330000,
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- .mapping = &cpg_mapping,
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-};
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-
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-static unsigned long pll_recalc(struct clk *clk)
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-{
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- return clk->parent->rate * PLL_RATE;
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-}
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-
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-static struct sh_clk_ops pll_clk_ops = {
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- .recalc = pll_recalc,
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-};
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-
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-static struct clk pll_clk = {
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- .ops = &pll_clk_ops,
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- .parent = &extal_clk,
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- .flags = CLK_ENABLE_ON_INIT,
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-};
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-
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-static unsigned long bus_recalc(struct clk *clk)
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-{
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- return clk->parent->rate / 3;
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-}
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-
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-static struct sh_clk_ops bus_clk_ops = {
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- .recalc = bus_recalc,
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-};
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-
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-static struct clk bus_clk = {
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- .ops = &bus_clk_ops,
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- .parent = &pll_clk,
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- .flags = CLK_ENABLE_ON_INIT,
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-};
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-
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-static unsigned long peripheral0_recalc(struct clk *clk)
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-{
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- return clk->parent->rate / 12;
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-}
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-
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-static struct sh_clk_ops peripheral0_clk_ops = {
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- .recalc = peripheral0_recalc,
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-};
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-
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-static struct clk peripheral0_clk = {
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- .ops = &peripheral0_clk_ops,
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- .parent = &pll_clk,
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- .flags = CLK_ENABLE_ON_INIT,
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-};
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-
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-static unsigned long peripheral1_recalc(struct clk *clk)
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-{
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- return clk->parent->rate / 6;
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-}
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-
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-static struct sh_clk_ops peripheral1_clk_ops = {
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- .recalc = peripheral1_recalc,
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-};
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-
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-static struct clk peripheral1_clk = {
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- .ops = &peripheral1_clk_ops,
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- .parent = &pll_clk,
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- .flags = CLK_ENABLE_ON_INIT,
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-};
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-
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-struct clk *main_clks[] = {
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- &r_clk,
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- &extal_clk,
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- &pll_clk,
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- &bus_clk,
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- &peripheral0_clk,
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- &peripheral1_clk,
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-};
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-
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-static int div2[] = { 1, 3, 0, 3 }; /* 1, 2/3, reserve, 1/3 */
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-static int multipliers[] = { 1, 2, 1, 1 };
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-
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-static struct clk_div_mult_table div4_div_mult_table = {
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- .divisors = div2,
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- .nr_divisors = ARRAY_SIZE(div2),
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- .multipliers = multipliers,
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- .nr_multipliers = ARRAY_SIZE(multipliers),
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-};
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-
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-static struct clk_div4_table div4_table = {
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- .div_mult_table = &div4_div_mult_table,
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-};
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-
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-enum { DIV4_I,
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- DIV4_NR };
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-
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-#define DIV4(_reg, _bit, _mask, _flags) \
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- SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
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-
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-/* The mask field specifies the div2 entries that are valid */
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-struct clk div4_clks[DIV4_NR] = {
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- [DIV4_I] = DIV4(FRQCR, 8, 0xB, CLK_ENABLE_REG_16BIT
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- | CLK_ENABLE_ON_INIT),
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-};
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-
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-enum {
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- MSTP107, MSTP106, MSTP105, MSTP104, MSTP103,
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- MSTP97, MSTP96, MSTP95, MSTP94,
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- MSTP74,
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- MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40,
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- MSTP33, MSTP_NR
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-};
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-
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-static struct clk mstp_clks[MSTP_NR] = {
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- [MSTP107] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 7, 0), /* RSPI0 */
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- [MSTP106] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 6, 0), /* RSPI1 */
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- [MSTP105] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 5, 0), /* RSPI2 */
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- [MSTP104] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 4, 0), /* RSPI3 */
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- [MSTP103] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 3, 0), /* RSPI4 */
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- [MSTP97] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 7, 0), /* RIIC0 */
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- [MSTP96] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 6, 0), /* RIIC1 */
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- [MSTP95] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 5, 0), /* RIIC2 */
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- [MSTP94] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 4, 0), /* RIIC3 */
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- [MSTP74] = SH_CLK_MSTP8(&peripheral1_clk, STBCR7, 4, 0), /* Ether */
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- [MSTP47] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 7, 0), /* SCIF0 */
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- [MSTP46] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 6, 0), /* SCIF1 */
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- [MSTP45] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 5, 0), /* SCIF2 */
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- [MSTP44] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 4, 0), /* SCIF3 */
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- [MSTP43] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 3, 0), /* SCIF4 */
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- [MSTP42] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 2, 0), /* SCIF5 */
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- [MSTP41] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 1, 0), /* SCIF6 */
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- [MSTP40] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 0, 0), /* SCIF7 */
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- [MSTP33] = SH_CLK_MSTP8(&peripheral0_clk, STBCR3, 3, 0), /* MTU2 */
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-};
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-
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-static struct clk_lookup lookups[] = {
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- /* main clocks */
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- CLKDEV_CON_ID("rclk", &r_clk),
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- CLKDEV_CON_ID("extal", &extal_clk),
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- CLKDEV_CON_ID("pll_clk", &pll_clk),
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- CLKDEV_CON_ID("peripheral_clk", &peripheral1_clk),
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-
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- /* DIV4 clocks */
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- CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
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-
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- /* MSTP clocks */
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- CLKDEV_DEV_ID("rspi-rz.0", &mstp_clks[MSTP107]),
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- CLKDEV_DEV_ID("rspi-rz.1", &mstp_clks[MSTP106]),
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- CLKDEV_DEV_ID("rspi-rz.2", &mstp_clks[MSTP105]),
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- CLKDEV_DEV_ID("rspi-rz.3", &mstp_clks[MSTP104]),
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- CLKDEV_DEV_ID("rspi-rz.4", &mstp_clks[MSTP103]),
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- CLKDEV_DEV_ID("r7s72100-ether", &mstp_clks[MSTP74]),
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-
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- /* ICK */
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- CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP47]),
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- CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP46]),
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- CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP45]),
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- CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[MSTP44]),
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- CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[MSTP43]),
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- CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[MSTP42]),
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- CLKDEV_ICK_ID("sci_fck", "sh-sci.6", &mstp_clks[MSTP41]),
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- CLKDEV_ICK_ID("sci_fck", "sh-sci.7", &mstp_clks[MSTP40]),
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- CLKDEV_ICK_ID("fck", "sh-mtu2", &mstp_clks[MSTP33]),
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-};
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-
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-void __init r7s72100_clock_init(void)
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-{
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- int k, ret = 0;
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-
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- for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
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- ret = clk_register(main_clks[k]);
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-
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- clkdev_add_table(lookups, ARRAY_SIZE(lookups));
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-
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- if (!ret)
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- ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
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-
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- if (!ret)
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- ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
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-
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- if (!ret)
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- shmobile_clk_init();
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- else
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- panic("failed to setup rza1 clocks\n");
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-}
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Laurent Pinchart