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@@ -128,19 +128,17 @@ intel_i2c_reset(struct drm_i915_private *dev_priv)
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I915_WRITE(GMBUS4, 0);
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}
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-static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
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+static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv,
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+ bool enable)
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{
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u32 val;
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/* When using bit bashing for I2C, this bit needs to be set to 1 */
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- if (!IS_PINEVIEW(dev_priv))
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- return;
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-
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val = I915_READ(DSPCLK_GATE_D);
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- if (enable)
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- val |= DPCUNIT_CLOCK_GATE_DISABLE;
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+ if (!enable)
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+ val |= PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;
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else
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- val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
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+ val &= ~PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;
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I915_WRITE(DSPCLK_GATE_D, val);
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}
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@@ -221,7 +219,10 @@ intel_gpio_pre_xfer(struct i2c_adapter *adapter)
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struct drm_i915_private *dev_priv = bus->dev_priv;
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intel_i2c_reset(dev_priv);
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- intel_i2c_quirk_set(dev_priv, true);
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+
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+ if (IS_PINEVIEW(dev_priv))
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+ pnv_gmbus_clock_gating(dev_priv, false);
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+
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set_data(bus, 1);
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set_clock(bus, 1);
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udelay(I2C_RISEFALL_TIME);
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@@ -238,7 +239,9 @@ intel_gpio_post_xfer(struct i2c_adapter *adapter)
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set_data(bus, 1);
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set_clock(bus, 1);
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- intel_i2c_quirk_set(dev_priv, false);
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+
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+ if (IS_PINEVIEW(dev_priv))
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+ pnv_gmbus_clock_gating(dev_priv, true);
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}
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static void
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