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@@ -1309,108 +1309,105 @@ static void render_ring_cleanup(struct intel_engine_cs *engine)
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intel_fini_pipe_control(engine);
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}
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-static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req)
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+static int gen8_rcs_signal(struct drm_i915_gem_request *req)
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{
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- struct intel_ring *signaller = signaller_req->ring;
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- struct drm_i915_private *dev_priv = signaller_req->i915;
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+ struct intel_ring *ring = req->ring;
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+ struct drm_i915_private *dev_priv = req->i915;
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struct intel_engine_cs *waiter;
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enum intel_engine_id id;
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int ret, num_rings;
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num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
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- ret = intel_ring_begin(signaller_req, (num_rings-1) * 8);
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+ ret = intel_ring_begin(req, (num_rings-1) * 8);
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if (ret)
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return ret;
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for_each_engine_id(waiter, dev_priv, id) {
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- u64 gtt_offset =
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- signaller_req->engine->semaphore.signal_ggtt[id];
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+ u64 gtt_offset = req->engine->semaphore.signal_ggtt[id];
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if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
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continue;
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- intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
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- intel_ring_emit(signaller,
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+ intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
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+ intel_ring_emit(ring,
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PIPE_CONTROL_GLOBAL_GTT_IVB |
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PIPE_CONTROL_QW_WRITE |
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PIPE_CONTROL_CS_STALL);
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- intel_ring_emit(signaller, lower_32_bits(gtt_offset));
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- intel_ring_emit(signaller, upper_32_bits(gtt_offset));
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- intel_ring_emit(signaller, signaller_req->fence.seqno);
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- intel_ring_emit(signaller, 0);
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- intel_ring_emit(signaller,
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+ intel_ring_emit(ring, lower_32_bits(gtt_offset));
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+ intel_ring_emit(ring, upper_32_bits(gtt_offset));
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+ intel_ring_emit(ring, req->fence.seqno);
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+ intel_ring_emit(ring, 0);
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+ intel_ring_emit(ring,
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MI_SEMAPHORE_SIGNAL |
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MI_SEMAPHORE_TARGET(waiter->hw_id));
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- intel_ring_emit(signaller, 0);
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+ intel_ring_emit(ring, 0);
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}
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- intel_ring_advance(signaller);
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+ intel_ring_advance(ring);
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return 0;
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}
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-static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req)
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+static int gen8_xcs_signal(struct drm_i915_gem_request *req)
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{
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- struct intel_ring *signaller = signaller_req->ring;
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- struct drm_i915_private *dev_priv = signaller_req->i915;
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+ struct intel_ring *ring = req->ring;
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+ struct drm_i915_private *dev_priv = req->i915;
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struct intel_engine_cs *waiter;
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enum intel_engine_id id;
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int ret, num_rings;
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num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
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- ret = intel_ring_begin(signaller_req, (num_rings-1) * 6);
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+ ret = intel_ring_begin(req, (num_rings-1) * 6);
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if (ret)
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return ret;
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for_each_engine_id(waiter, dev_priv, id) {
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- u64 gtt_offset =
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- signaller_req->engine->semaphore.signal_ggtt[id];
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+ u64 gtt_offset = req->engine->semaphore.signal_ggtt[id];
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if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
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continue;
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- intel_ring_emit(signaller,
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+ intel_ring_emit(ring,
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(MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW);
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- intel_ring_emit(signaller,
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+ intel_ring_emit(ring,
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lower_32_bits(gtt_offset) |
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MI_FLUSH_DW_USE_GTT);
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- intel_ring_emit(signaller, upper_32_bits(gtt_offset));
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- intel_ring_emit(signaller, signaller_req->fence.seqno);
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- intel_ring_emit(signaller,
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+ intel_ring_emit(ring, upper_32_bits(gtt_offset));
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+ intel_ring_emit(ring, req->fence.seqno);
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+ intel_ring_emit(ring,
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MI_SEMAPHORE_SIGNAL |
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MI_SEMAPHORE_TARGET(waiter->hw_id));
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- intel_ring_emit(signaller, 0);
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+ intel_ring_emit(ring, 0);
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}
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- intel_ring_advance(signaller);
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+ intel_ring_advance(ring);
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return 0;
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}
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-static int gen6_signal(struct drm_i915_gem_request *signaller_req)
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+static int gen6_signal(struct drm_i915_gem_request *req)
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{
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- struct intel_ring *signaller = signaller_req->ring;
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- struct drm_i915_private *dev_priv = signaller_req->i915;
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+ struct intel_ring *ring = req->ring;
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+ struct drm_i915_private *dev_priv = req->i915;
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struct intel_engine_cs *useless;
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enum intel_engine_id id;
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int ret, num_rings;
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num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
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- ret = intel_ring_begin(signaller_req, round_up((num_rings-1) * 3, 2));
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+ ret = intel_ring_begin(req, round_up((num_rings-1) * 3, 2));
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if (ret)
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return ret;
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for_each_engine_id(useless, dev_priv, id) {
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- i915_reg_t mbox_reg =
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- signaller_req->engine->semaphore.mbox.signal[id];
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+ i915_reg_t mbox_reg = req->engine->semaphore.mbox.signal[id];
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if (i915_mmio_reg_valid(mbox_reg)) {
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- intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
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- intel_ring_emit_reg(signaller, mbox_reg);
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- intel_ring_emit(signaller, signaller_req->fence.seqno);
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+ intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
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+ intel_ring_emit_reg(ring, mbox_reg);
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+ intel_ring_emit(ring, req->fence.seqno);
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}
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}
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/* If num_dwords was rounded, make sure the tail pointer is correct */
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if (num_rings % 2 == 0)
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- intel_ring_emit(signaller, MI_NOOP);
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- intel_ring_advance(signaller);
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+ intel_ring_emit(ring, MI_NOOP);
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+ intel_ring_advance(ring);
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return 0;
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}
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@@ -1505,64 +1502,65 @@ static int gen8_render_emit_request(struct drm_i915_gem_request *req)
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*/
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static int
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-gen8_ring_sync(struct drm_i915_gem_request *wait,
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- struct drm_i915_gem_request *signal)
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+gen8_ring_sync_to(struct drm_i915_gem_request *req,
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+ struct drm_i915_gem_request *signal)
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{
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- struct intel_ring *waiter = wait->ring;
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- struct drm_i915_private *dev_priv = wait->i915;
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- u64 offset = GEN8_WAIT_OFFSET(wait->engine, signal->engine->id);
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+ struct intel_ring *ring = req->ring;
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+ struct drm_i915_private *dev_priv = req->i915;
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+ u64 offset = GEN8_WAIT_OFFSET(req->engine, signal->engine->id);
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struct i915_hw_ppgtt *ppgtt;
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int ret;
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- ret = intel_ring_begin(wait, 4);
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+ ret = intel_ring_begin(req, 4);
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if (ret)
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return ret;
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- intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
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- MI_SEMAPHORE_GLOBAL_GTT |
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- MI_SEMAPHORE_SAD_GTE_SDD);
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- intel_ring_emit(waiter, signal->fence.seqno);
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- intel_ring_emit(waiter, lower_32_bits(offset));
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- intel_ring_emit(waiter, upper_32_bits(offset));
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- intel_ring_advance(waiter);
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+ intel_ring_emit(ring,
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+ MI_SEMAPHORE_WAIT |
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+ MI_SEMAPHORE_GLOBAL_GTT |
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+ MI_SEMAPHORE_SAD_GTE_SDD);
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+ intel_ring_emit(ring, signal->fence.seqno);
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+ intel_ring_emit(ring, lower_32_bits(offset));
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+ intel_ring_emit(ring, upper_32_bits(offset));
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+ intel_ring_advance(ring);
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/* When the !RCS engines idle waiting upon a semaphore, they lose their
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* pagetables and we must reload them before executing the batch.
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* We do this on the i915_switch_context() following the wait and
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* before the dispatch.
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*/
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- ppgtt = wait->ctx->ppgtt;
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- if (ppgtt && wait->engine->id != RCS)
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- ppgtt->pd_dirty_rings |= intel_engine_flag(wait->engine);
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+ ppgtt = req->ctx->ppgtt;
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+ if (ppgtt && req->engine->id != RCS)
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+ ppgtt->pd_dirty_rings |= intel_engine_flag(req->engine);
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return 0;
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}
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static int
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-gen6_ring_sync(struct drm_i915_gem_request *wait,
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- struct drm_i915_gem_request *signal)
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+gen6_ring_sync_to(struct drm_i915_gem_request *req,
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+ struct drm_i915_gem_request *signal)
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{
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- struct intel_ring *waiter = wait->ring;
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+ struct intel_ring *ring = req->ring;
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u32 dw1 = MI_SEMAPHORE_MBOX |
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MI_SEMAPHORE_COMPARE |
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MI_SEMAPHORE_REGISTER;
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- u32 wait_mbox = signal->engine->semaphore.mbox.wait[wait->engine->id];
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+ u32 wait_mbox = signal->engine->semaphore.mbox.wait[req->engine->id];
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int ret;
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WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
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- ret = intel_ring_begin(wait, 4);
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+ ret = intel_ring_begin(req, 4);
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if (ret)
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return ret;
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- intel_ring_emit(waiter, dw1 | wait_mbox);
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+ intel_ring_emit(ring, dw1 | wait_mbox);
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/* Throughout all of the GEM code, seqno passed implies our current
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* seqno is >= the last seqno executed. However for hardware the
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* comparison is strictly greater than.
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*/
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- intel_ring_emit(waiter, signal->fence.seqno - 1);
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- intel_ring_emit(waiter, 0);
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- intel_ring_emit(waiter, MI_NOOP);
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- intel_ring_advance(waiter);
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+ intel_ring_emit(ring, signal->fence.seqno - 1);
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+ intel_ring_emit(ring, 0);
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+ intel_ring_emit(ring, MI_NOOP);
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+ intel_ring_advance(ring);
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return 0;
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}
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@@ -2669,7 +2667,7 @@ static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv,
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if (INTEL_GEN(dev_priv) >= 8) {
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u64 offset = i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj);
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- engine->semaphore.sync_to = gen8_ring_sync;
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+ engine->semaphore.sync_to = gen8_ring_sync_to;
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engine->semaphore.signal = gen8_xcs_signal;
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for (i = 0; i < I915_NUM_ENGINES; i++) {
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@@ -2683,7 +2681,7 @@ static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv,
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engine->semaphore.signal_ggtt[i] = ring_offset;
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}
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} else if (INTEL_GEN(dev_priv) >= 6) {
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- engine->semaphore.sync_to = gen6_ring_sync;
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+ engine->semaphore.sync_to = gen6_ring_sync_to;
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engine->semaphore.signal = gen6_signal;
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/*
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