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@@ -593,7 +593,7 @@ static u32 ar9003_mci_wait_for_gpm(struct ath_hw *ah, u8 gpm_type,
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if (!time_out)
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break;
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- offset = ar9003_mci_get_next_gpm_offset(ah, false, &more_data);
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+ offset = ar9003_mci_get_next_gpm_offset(ah, &more_data);
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if (offset == MCI_GPM_INVALID)
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continue;
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@@ -657,7 +657,7 @@ static u32 ar9003_mci_wait_for_gpm(struct ath_hw *ah, u8 gpm_type,
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time_out = 0;
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while (more_data == MCI_GPM_MORE) {
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- offset = ar9003_mci_get_next_gpm_offset(ah, false, &more_data);
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+ offset = ar9003_mci_get_next_gpm_offset(ah, &more_data);
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if (offset == MCI_GPM_INVALID)
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break;
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@@ -986,7 +986,8 @@ int ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g,
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regval &= ~SM(1, AR_MCI_COMMAND2_RESET_RX);
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REG_WRITE(ah, AR_MCI_COMMAND2, regval);
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- ar9003_mci_get_next_gpm_offset(ah, true, NULL);
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+ /* Init GPM offset after MCI Reset Rx */
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+ ar9003_mci_state(ah, MCI_STATE_INIT_GPM_OFFSET);
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REG_WRITE(ah, AR_MCI_MSG_ATTRIBUTES_TABLE,
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(SM(0xe801, AR_MCI_MSG_ATTRIBUTES_TABLE_INVALID_HDR) |
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@@ -1280,6 +1281,14 @@ u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type)
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}
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value &= AR_BTCOEX_CTRL_MCI_MODE_EN;
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break;
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+ case MCI_STATE_INIT_GPM_OFFSET:
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+ value = MS(REG_READ(ah, AR_MCI_GPM_1), AR_MCI_GPM_WRITE_PTR);
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+
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+ if (value < mci->gpm_len)
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+ mci->gpm_idx = value;
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+ else
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+ mci->gpm_idx = 0;
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+ break;
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case MCI_STATE_LAST_SCHD_MSG_OFFSET:
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value = MS(REG_READ(ah, AR_MCI_RX_STATUS),
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AR_MCI_RX_LAST_SCHD_MSG_INDEX);
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@@ -1426,21 +1435,11 @@ void ar9003_mci_check_gpm_offset(struct ath_hw *ah)
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mci->gpm_idx = 0;
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}
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-u32 ar9003_mci_get_next_gpm_offset(struct ath_hw *ah, bool first, u32 *more)
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+u32 ar9003_mci_get_next_gpm_offset(struct ath_hw *ah, u32 *more)
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{
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struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
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u32 offset, more_gpm = 0, gpm_ptr;
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- if (first) {
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- gpm_ptr = MS(REG_READ(ah, AR_MCI_GPM_1), AR_MCI_GPM_WRITE_PTR);
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-
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- if (gpm_ptr >= mci->gpm_len)
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- gpm_ptr = 0;
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-
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- mci->gpm_idx = gpm_ptr;
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- return gpm_ptr;
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- }
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-
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/*
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* This could be useful to avoid new GPM message interrupt which
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* may lead to spurious interrupt after power sleep, or multiple
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