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@@ -766,6 +766,67 @@ static struct cpuidle_state knl_cstates[] = {
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.enter = NULL }
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};
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+static struct cpuidle_state bxt_cstates[] = {
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+ {
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+ .name = "C1-BXT",
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+ .desc = "MWAIT 0x00",
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+ .flags = MWAIT2flg(0x00),
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+ .exit_latency = 2,
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+ .target_residency = 2,
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+ .enter = &intel_idle,
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+ .enter_freeze = intel_idle_freeze, },
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+ {
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+ .name = "C1E-BXT",
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+ .desc = "MWAIT 0x01",
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+ .flags = MWAIT2flg(0x01),
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+ .exit_latency = 10,
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+ .target_residency = 20,
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+ .enter = &intel_idle,
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+ .enter_freeze = intel_idle_freeze, },
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+ {
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+ .name = "C6-BXT",
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+ .desc = "MWAIT 0x20",
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+ .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
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+ .exit_latency = 133,
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+ .target_residency = 133,
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+ .enter = &intel_idle,
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+ .enter_freeze = intel_idle_freeze, },
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+ {
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+ .name = "C7s-BXT",
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+ .desc = "MWAIT 0x31",
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+ .flags = MWAIT2flg(0x31) | CPUIDLE_FLAG_TLB_FLUSHED,
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+ .exit_latency = 155,
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+ .target_residency = 155,
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+ .enter = &intel_idle,
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+ .enter_freeze = intel_idle_freeze, },
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+ {
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+ .name = "C8-BXT",
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+ .desc = "MWAIT 0x40",
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+ .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
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+ .exit_latency = 1000,
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+ .target_residency = 1000,
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+ .enter = &intel_idle,
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+ .enter_freeze = intel_idle_freeze, },
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+ {
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+ .name = "C9-BXT",
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+ .desc = "MWAIT 0x50",
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+ .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
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+ .exit_latency = 2000,
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+ .target_residency = 2000,
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+ .enter = &intel_idle,
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+ .enter_freeze = intel_idle_freeze, },
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+ {
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+ .name = "C10-BXT",
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+ .desc = "MWAIT 0x60",
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+ .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
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+ .exit_latency = 10000,
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+ .target_residency = 10000,
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+ .enter = &intel_idle,
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+ .enter_freeze = intel_idle_freeze, },
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+ {
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+ .enter = NULL }
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+};
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+
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/**
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* intel_idle
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* @dev: cpuidle_device
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@@ -950,6 +1011,11 @@ static const struct idle_cpu idle_cpu_knl = {
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.state_table = knl_cstates,
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};
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+static const struct idle_cpu idle_cpu_bxt = {
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+ .state_table = bxt_cstates,
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+ .disable_promotion_to_c1e = true,
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+};
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+
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#define ICPU(model, cpu) \
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{ X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (unsigned long)&cpu }
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@@ -985,6 +1051,7 @@ static const struct x86_cpu_id intel_idle_ids[] __initconst = {
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ICPU(0x9e, idle_cpu_skl),
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ICPU(0x55, idle_cpu_skx),
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ICPU(0x57, idle_cpu_knl),
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+ ICPU(0x5c, idle_cpu_bxt),
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{}
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};
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MODULE_DEVICE_TABLE(x86cpu, intel_idle_ids);
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@@ -1075,6 +1142,73 @@ static void ivt_idle_state_table_update(void)
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/* else, 1 and 2 socket systems use default ivt_cstates */
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}
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+
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+/*
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+ * Translate IRTL (Interrupt Response Time Limit) MSR to usec
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+ */
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+
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+static unsigned int irtl_ns_units[] = {
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+ 1, 32, 1024, 32768, 1048576, 33554432, 0, 0 };
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+
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+static unsigned long long irtl_2_usec(unsigned long long irtl)
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+{
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+ unsigned long long ns;
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+
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+ ns = irtl_ns_units[(irtl >> 10) & 0x3];
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+
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+ return div64_u64((irtl & 0x3FF) * ns, 1000);
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+}
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+/*
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+ * bxt_idle_state_table_update(void)
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+ *
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+ * On BXT, we trust the IRTL to show the definitive maximum latency
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+ * We use the same value for target_residency.
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+ */
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+static void bxt_idle_state_table_update(void)
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+{
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+ unsigned long long msr;
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+
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+ rdmsrl(MSR_PKGC6_IRTL, msr);
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+ if (msr) {
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+ unsigned int usec = irtl_2_usec(msr);
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+
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+ bxt_cstates[2].exit_latency = usec;
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+ bxt_cstates[2].target_residency = usec;
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+ }
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+
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+ rdmsrl(MSR_PKGC7_IRTL, msr);
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+ if (msr) {
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+ unsigned int usec = irtl_2_usec(msr);
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+
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+ bxt_cstates[3].exit_latency = usec;
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+ bxt_cstates[3].target_residency = usec;
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+ }
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+
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+ rdmsrl(MSR_PKGC8_IRTL, msr);
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+ if (msr) {
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+ unsigned int usec = irtl_2_usec(msr);
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+
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+ bxt_cstates[4].exit_latency = usec;
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+ bxt_cstates[4].target_residency = usec;
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+ }
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+
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+ rdmsrl(MSR_PKGC9_IRTL, msr);
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+ if (msr) {
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+ unsigned int usec = irtl_2_usec(msr);
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+
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+ bxt_cstates[5].exit_latency = usec;
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+ bxt_cstates[5].target_residency = usec;
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+ }
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+
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+ rdmsrl(MSR_PKGC10_IRTL, msr);
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+ if (msr) {
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+ unsigned int usec = irtl_2_usec(msr);
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+
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+ bxt_cstates[6].exit_latency = usec;
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+ bxt_cstates[6].target_residency = usec;
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+ }
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+
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+}
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/*
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* sklh_idle_state_table_update(void)
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*
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@@ -1130,6 +1264,9 @@ static void intel_idle_state_table_update(void)
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case 0x3e: /* IVT */
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ivt_idle_state_table_update();
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break;
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+ case 0x5c: /* BXT */
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+ bxt_idle_state_table_update();
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+ break;
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case 0x5e: /* SKL-H */
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sklh_idle_state_table_update();
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break;
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