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@@ -4418,11 +4418,12 @@ static int cik_mec_init(struct radeon_device *rdev)
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/*
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* KV: 2 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 64 Queues total
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* CI/KB: 1 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 32 Queues total
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- * Nonetheless, we assign only 1 pipe because all other pipes will
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- * be handled by KFD
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*/
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- rdev->mec.num_mec = 1;
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- rdev->mec.num_pipe = 1;
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+ if (rdev->family == CHIP_KAVERI)
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+ rdev->mec.num_mec = 2;
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+ else
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+ rdev->mec.num_mec = 1;
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+ rdev->mec.num_pipe = 4;
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rdev->mec.num_queue = rdev->mec.num_mec * rdev->mec.num_pipe * 8;
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if (rdev->mec.hpd_eop_obj == NULL) {
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@@ -4565,8 +4566,11 @@ static int cik_cp_compute_resume(struct radeon_device *rdev)
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/* init the pipes */
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mutex_lock(&rdev->srbm_mutex);
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- for (i = 0; i < rdev->mec.num_pipe; ++i) {
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- cik_srbm_select(rdev, 0, i, 0, 0);
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+ for (i = 0; i < (rdev->mec.num_pipe * rdev->mec.num_mec); ++i) {
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+ int me = (i < 4) ? 1 : 2;
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+ int pipe = (i < 4) ? i : (i - 4);
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+
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+ cik_srbm_select(rdev, me, pipe, 0, 0);
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eop_gpu_addr = rdev->mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE * 2) ;
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/* write the EOP addr */
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@@ -4583,6 +4587,7 @@ static int cik_cp_compute_resume(struct radeon_device *rdev)
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WREG32(CP_HPD_EOP_CONTROL, tmp);
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}
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+ cik_srbm_select(rdev, 0, 0, 0, 0);
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mutex_unlock(&rdev->srbm_mutex);
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/* init the queues. Just two for now. */
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