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@@ -19,6 +19,7 @@ static void __init h8300_div_clk_setup(struct device_node *node)
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const char *parent_name;
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void __iomem *divcr = NULL;
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int width;
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+ int offset;
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num_parents = of_clk_get_parent_count(node);
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if (num_parents < 1) {
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@@ -31,11 +32,14 @@ static void __init h8300_div_clk_setup(struct device_node *node)
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pr_err("%s: failed to map divide register", clk_name);
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goto error;
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}
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+ offset = (unsigned long)divcr & 3;
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+ offset = (3 - offset) * 8;
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+ divcr = (void *)((unsigned long)divcr & ~3);
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parent_name = of_clk_get_parent_name(node, 0);
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of_property_read_u32(node, "renesas,width", &width);
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clk = clk_register_divider(NULL, clk_name, parent_name,
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- CLK_SET_RATE_GATE, divcr, 0, width,
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+ CLK_SET_RATE_GATE, divcr, offset, width,
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CLK_DIVIDER_POWER_OF_TWO, &clklock);
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if (!IS_ERR(clk)) {
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of_clk_add_provider(node, of_clk_src_simple_get, clk);
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