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@@ -13303,6 +13303,16 @@ intel_check_primary_plane(struct drm_plane *plane,
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intel_crtc->atomic.wait_vblank = true;
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}
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+ /*
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+ * FIXME: Actually if we will still have any other plane enabled
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+ * on the pipe we could let IPS enabled still, but for
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+ * now lets consider that when we make primary invisible
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+ * by setting DSPCNTR to 0 on update_primary_plane function
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+ * IPS needs to be disable.
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+ */
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+ if (!state->visible || !fb)
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+ intel_crtc->atomic.disable_ips = true;
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+
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intel_crtc->atomic.fb_bits |=
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INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
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@@ -13400,6 +13410,9 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc)
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if (intel_crtc->atomic.disable_fbc)
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intel_fbc_disable(dev);
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+ if (intel_crtc->atomic.disable_ips)
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+ hsw_disable_ips(intel_crtc);
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+
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if (intel_crtc->atomic.pre_disable_primary)
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intel_pre_disable_primary(crtc);
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