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@@ -0,0 +1,518 @@
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+/**
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+ * 1588 PTP support for Cadence GEM device.
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+ *
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+ * Copyright (C) 2017 Cadence Design Systems - http://www.cadence.com
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+ *
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+ * Authors: Rafal Ozieblo <rafalo@cadence.com>
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+ * Bartosz Folta <bfolta@cadence.com>
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+ *
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+ * This program is free software: you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 of
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+ * the License as published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
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+ */
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+#include <linux/kernel.h>
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+#include <linux/types.h>
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+#include <linux/clk.h>
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+#include <linux/device.h>
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+#include <linux/etherdevice.h>
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+#include <linux/platform_device.h>
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+#include <linux/time64.h>
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+#include <linux/ptp_classify.h>
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+#include <linux/if_ether.h>
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+#include <linux/if_vlan.h>
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+#include <linux/net_tstamp.h>
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+#include <linux/circ_buf.h>
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+#include <linux/spinlock.h>
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+
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+#include "macb.h"
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+
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+#define GEM_PTP_TIMER_NAME "gem-ptp-timer"
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+
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+static struct macb_dma_desc_ptp *macb_ptp_desc(struct macb *bp,
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+ struct macb_dma_desc *desc)
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+{
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+ if (bp->hw_dma_cap == HW_DMA_CAP_PTP)
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+ return (struct macb_dma_desc_ptp *)
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+ ((u8 *)desc + sizeof(struct macb_dma_desc));
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+ if (bp->hw_dma_cap == HW_DMA_CAP_64B_PTP)
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+ return (struct macb_dma_desc_ptp *)
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+ ((u8 *)desc + sizeof(struct macb_dma_desc)
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+ + sizeof(struct macb_dma_desc_64));
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+ return NULL;
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+}
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+
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+static int gem_tsu_get_time(struct ptp_clock_info *ptp, struct timespec64 *ts)
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+{
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+ struct macb *bp = container_of(ptp, struct macb, ptp_clock_info);
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+ unsigned long flags;
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+ long first, second;
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+ u32 secl, sech;
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+
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+ spin_lock_irqsave(&bp->tsu_clk_lock, flags);
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+ first = gem_readl(bp, TN);
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+ secl = gem_readl(bp, TSL);
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+ sech = gem_readl(bp, TSH);
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+ second = gem_readl(bp, TN);
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+
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+ /* test for nsec rollover */
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+ if (first > second) {
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+ /* if so, use later read & re-read seconds
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+ * (assume all done within 1s)
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+ */
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+ ts->tv_nsec = gem_readl(bp, TN);
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+ secl = gem_readl(bp, TSL);
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+ sech = gem_readl(bp, TSH);
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+ } else {
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+ ts->tv_nsec = first;
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+ }
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+
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+ spin_unlock_irqrestore(&bp->tsu_clk_lock, flags);
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+ ts->tv_sec = (((u64)sech << GEM_TSL_SIZE) | secl)
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+ & TSU_SEC_MAX_VAL;
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+ return 0;
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+}
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+
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+static int gem_tsu_set_time(struct ptp_clock_info *ptp,
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+ const struct timespec64 *ts)
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+{
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+ struct macb *bp = container_of(ptp, struct macb, ptp_clock_info);
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+ unsigned long flags;
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+ u32 ns, sech, secl;
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+
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+ secl = (u32)ts->tv_sec;
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+ sech = (ts->tv_sec >> GEM_TSL_SIZE) & ((1 << GEM_TSH_SIZE) - 1);
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+ ns = ts->tv_nsec;
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+
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+ spin_lock_irqsave(&bp->tsu_clk_lock, flags);
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+
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+ /* TSH doesn't latch the time and no atomicity! */
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+ gem_writel(bp, TN, 0); /* clear to avoid overflow */
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+ gem_writel(bp, TSH, sech);
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+ /* write lower bits 2nd, for synchronized secs update */
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+ gem_writel(bp, TSL, secl);
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+ gem_writel(bp, TN, ns);
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+
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+ spin_unlock_irqrestore(&bp->tsu_clk_lock, flags);
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+
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+ return 0;
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+}
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+
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+static int gem_tsu_incr_set(struct macb *bp, struct tsu_incr *incr_spec)
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+{
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+ unsigned long flags;
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+
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+ /* tsu_timer_incr register must be written after
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+ * the tsu_timer_incr_sub_ns register and the write operation
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+ * will cause the value written to the tsu_timer_incr_sub_ns register
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+ * to take effect.
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+ */
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+ spin_lock_irqsave(&bp->tsu_clk_lock, flags);
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+ gem_writel(bp, TISUBN, GEM_BF(SUBNSINCR, incr_spec->sub_ns));
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+ gem_writel(bp, TI, GEM_BF(NSINCR, incr_spec->ns));
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+ spin_unlock_irqrestore(&bp->tsu_clk_lock, flags);
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+
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+ return 0;
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+}
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+
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+static int gem_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
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+{
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+ struct macb *bp = container_of(ptp, struct macb, ptp_clock_info);
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+ struct tsu_incr incr_spec;
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+ bool neg_adj = false;
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+ u32 word;
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+ u64 adj;
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+
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+ if (scaled_ppm < 0) {
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+ neg_adj = true;
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+ scaled_ppm = -scaled_ppm;
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+ }
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+
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+ /* Adjustment is relative to base frequency */
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+ incr_spec.sub_ns = bp->tsu_incr.sub_ns;
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+ incr_spec.ns = bp->tsu_incr.ns;
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+
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+ /* scaling: unused(8bit) | ns(8bit) | fractions(16bit) */
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+ word = ((u64)incr_spec.ns << GEM_SUBNSINCR_SIZE) + incr_spec.sub_ns;
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+ adj = (u64)scaled_ppm * word;
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+ /* Divide with rounding, equivalent to floating dividing:
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+ * (temp / USEC_PER_SEC) + 0.5
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+ */
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+ adj += (USEC_PER_SEC >> 1);
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+ adj >>= GEM_SUBNSINCR_SIZE; /* remove fractions */
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+ adj = div_u64(adj, USEC_PER_SEC);
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+ adj = neg_adj ? (word - adj) : (word + adj);
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+
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+ incr_spec.ns = (adj >> GEM_SUBNSINCR_SIZE)
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+ & ((1 << GEM_NSINCR_SIZE) - 1);
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+ incr_spec.sub_ns = adj & ((1 << GEM_SUBNSINCR_SIZE) - 1);
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+ gem_tsu_incr_set(bp, &incr_spec);
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+ return 0;
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+}
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+
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+static int gem_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
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+{
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+ struct macb *bp = container_of(ptp, struct macb, ptp_clock_info);
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+ struct timespec64 now, then = ns_to_timespec64(delta);
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+ u32 adj, sign = 0;
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+
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+ if (delta < 0) {
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+ sign = 1;
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+ delta = -delta;
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+ }
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+
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+ if (delta > TSU_NSEC_MAX_VAL) {
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+ gem_tsu_get_time(&bp->ptp_clock_info, &now);
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+ if (sign)
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+ now = timespec64_sub(now, then);
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+ else
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+ now = timespec64_add(now, then);
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+
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+ gem_tsu_set_time(&bp->ptp_clock_info,
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+ (const struct timespec64 *)&now);
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+ } else {
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+ adj = (sign << GEM_ADDSUB_OFFSET) | delta;
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+
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+ gem_writel(bp, TA, adj);
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+ }
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+
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+ return 0;
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+}
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+
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+static int gem_ptp_enable(struct ptp_clock_info *ptp,
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+ struct ptp_clock_request *rq, int on)
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+{
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+ return -EOPNOTSUPP;
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+}
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+
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+static struct ptp_clock_info gem_ptp_caps_template = {
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+ .owner = THIS_MODULE,
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+ .name = GEM_PTP_TIMER_NAME,
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+ .max_adj = 0,
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+ .n_alarm = 0,
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+ .n_ext_ts = 0,
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+ .n_per_out = 0,
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+ .n_pins = 0,
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+ .pps = 1,
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+ .adjfine = gem_ptp_adjfine,
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+ .adjtime = gem_ptp_adjtime,
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+ .gettime64 = gem_tsu_get_time,
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+ .settime64 = gem_tsu_set_time,
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+ .enable = gem_ptp_enable,
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+};
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+
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+static void gem_ptp_init_timer(struct macb *bp)
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+{
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+ u32 rem = 0;
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+ u64 adj;
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+
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+ bp->tsu_incr.ns = div_u64_rem(NSEC_PER_SEC, bp->tsu_rate, &rem);
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+ if (rem) {
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+ adj = rem;
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+ adj <<= GEM_SUBNSINCR_SIZE;
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+ bp->tsu_incr.sub_ns = div_u64(adj, bp->tsu_rate);
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+ } else {
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+ bp->tsu_incr.sub_ns = 0;
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+ }
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+}
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+
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+static void gem_ptp_init_tsu(struct macb *bp)
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+{
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+ struct timespec64 ts;
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+
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+ /* 1. get current system time */
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+ ts = ns_to_timespec64(ktime_to_ns(ktime_get_real()));
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+
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+ /* 2. set ptp timer */
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+ gem_tsu_set_time(&bp->ptp_clock_info, &ts);
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+
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+ /* 3. set PTP timer increment value to BASE_INCREMENT */
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+ gem_tsu_incr_set(bp, &bp->tsu_incr);
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+
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+ gem_writel(bp, TA, 0);
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+}
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+
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+static void gem_ptp_clear_timer(struct macb *bp)
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+{
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+ bp->tsu_incr.sub_ns = 0;
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+ bp->tsu_incr.ns = 0;
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+
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+ gem_writel(bp, TISUBN, GEM_BF(SUBNSINCR, 0));
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+ gem_writel(bp, TI, GEM_BF(NSINCR, 0));
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+ gem_writel(bp, TA, 0);
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+}
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+
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+static int gem_hw_timestamp(struct macb *bp, u32 dma_desc_ts_1,
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+ u32 dma_desc_ts_2, struct timespec64 *ts)
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+{
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+ struct timespec64 tsu;
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+
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+ ts->tv_sec = (GEM_BFEXT(DMA_SECH, dma_desc_ts_2) << GEM_DMA_SECL_SIZE) |
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+ GEM_BFEXT(DMA_SECL, dma_desc_ts_1);
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+ ts->tv_nsec = GEM_BFEXT(DMA_NSEC, dma_desc_ts_1);
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+
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+ /* TSU overlapping workaround
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+ * The timestamp only contains lower few bits of seconds,
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+ * so add value from 1588 timer
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+ */
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+ gem_tsu_get_time(&bp->ptp_clock_info, &tsu);
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+
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+ /* If the top bit is set in the timestamp,
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+ * but not in 1588 timer, it has rolled over,
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+ * so subtract max size
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+ */
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+ if ((ts->tv_sec & (GEM_DMA_SEC_TOP >> 1)) &&
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+ !(tsu.tv_sec & (GEM_DMA_SEC_TOP >> 1)))
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+ ts->tv_sec -= GEM_DMA_SEC_TOP;
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+
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+ ts->tv_sec += ((~GEM_DMA_SEC_MASK) & tsu.tv_sec);
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+
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+ return 0;
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+}
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+
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+void gem_ptp_rxstamp(struct macb *bp, struct sk_buff *skb,
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+ struct macb_dma_desc *desc)
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+{
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+ struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
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+ struct macb_dma_desc_ptp *desc_ptp;
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+ struct timespec64 ts;
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+
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+ if (GEM_BFEXT(DMA_RXVALID, desc->addr)) {
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+ desc_ptp = macb_ptp_desc(bp, desc);
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+ gem_hw_timestamp(bp, desc_ptp->ts_1, desc_ptp->ts_2, &ts);
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+ memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps));
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+ shhwtstamps->hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec);
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+ }
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+}
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+
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+static void gem_tstamp_tx(struct macb *bp, struct sk_buff *skb,
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+ struct macb_dma_desc_ptp *desc_ptp)
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+{
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+ struct skb_shared_hwtstamps shhwtstamps;
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+ struct timespec64 ts;
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+
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+ gem_hw_timestamp(bp, desc_ptp->ts_1, desc_ptp->ts_2, &ts);
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+ memset(&shhwtstamps, 0, sizeof(shhwtstamps));
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+ shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec);
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+ skb_tstamp_tx(skb, &shhwtstamps);
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+}
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+
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+int gem_ptp_txstamp(struct macb_queue *queue, struct sk_buff *skb,
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+ struct macb_dma_desc *desc)
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+{
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+ unsigned long tail = READ_ONCE(queue->tx_ts_tail);
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+ unsigned long head = queue->tx_ts_head;
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+ struct macb_dma_desc_ptp *desc_ptp;
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+ struct gem_tx_ts *tx_timestamp;
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+
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+ if (!GEM_BFEXT(DMA_TXVALID, desc->ctrl))
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+ return -EINVAL;
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+
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+ if (CIRC_SPACE(head, tail, PTP_TS_BUFFER_SIZE) == 0)
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+ return -ENOMEM;
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+
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+ skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
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+ desc_ptp = macb_ptp_desc(queue->bp, desc);
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+ tx_timestamp = &queue->tx_timestamps[head];
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+ tx_timestamp->skb = skb;
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+ tx_timestamp->desc_ptp.ts_1 = desc_ptp->ts_1;
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+ tx_timestamp->desc_ptp.ts_2 = desc_ptp->ts_2;
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+ /* move head */
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+ smp_store_release(&queue->tx_ts_head,
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+ (head + 1) & (PTP_TS_BUFFER_SIZE - 1));
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+
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+ schedule_work(&queue->tx_ts_task);
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+ return 0;
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+}
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+
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+static void gem_tx_timestamp_flush(struct work_struct *work)
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+{
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+ struct macb_queue *queue =
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+ container_of(work, struct macb_queue, tx_ts_task);
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+ unsigned long head, tail;
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+ struct gem_tx_ts *tx_ts;
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+
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+ /* take current head */
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+ head = smp_load_acquire(&queue->tx_ts_head);
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+ tail = queue->tx_ts_tail;
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+
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+ while (CIRC_CNT(head, tail, PTP_TS_BUFFER_SIZE)) {
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+ tx_ts = &queue->tx_timestamps[tail];
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+ gem_tstamp_tx(queue->bp, tx_ts->skb, &tx_ts->desc_ptp);
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+ /* cleanup */
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+ dev_kfree_skb_any(tx_ts->skb);
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+ /* remove old tail */
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+ smp_store_release(&queue->tx_ts_tail,
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+ (tail + 1) & (PTP_TS_BUFFER_SIZE - 1));
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+ tail = queue->tx_ts_tail;
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+ }
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+}
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+
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+void gem_ptp_init(struct net_device *dev)
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+{
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+ struct macb *bp = netdev_priv(dev);
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+ struct macb_queue *queue;
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+ unsigned int q;
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+
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+ bp->ptp_clock_info = gem_ptp_caps_template;
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+
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+ /* nominal frequency and maximum adjustment in ppb */
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+ bp->tsu_rate = bp->ptp_info->get_tsu_rate(bp);
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+ bp->ptp_clock_info.max_adj = bp->ptp_info->get_ptp_max_adj();
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+ gem_ptp_init_timer(bp);
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+ bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &dev->dev);
|
|
|
+ if (IS_ERR(bp->ptp_clock)) {
|
|
|
+ pr_err("ptp clock register failed: %ld\n",
|
|
|
+ PTR_ERR(bp->ptp_clock));
|
|
|
+ bp->ptp_clock = NULL;
|
|
|
+ return;
|
|
|
+ } else if (bp->ptp_clock == NULL) {
|
|
|
+ pr_err("ptp clock register failed\n");
|
|
|
+ return;
|
|
|
+ }
|
|
|
+
|
|
|
+ spin_lock_init(&bp->tsu_clk_lock);
|
|
|
+ for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
|
|
|
+ queue->tx_ts_head = 0;
|
|
|
+ queue->tx_ts_tail = 0;
|
|
|
+ INIT_WORK(&queue->tx_ts_task, gem_tx_timestamp_flush);
|
|
|
+ }
|
|
|
+
|
|
|
+ gem_ptp_init_tsu(bp);
|
|
|
+
|
|
|
+ dev_info(&bp->pdev->dev, "%s ptp clock registered.\n",
|
|
|
+ GEM_PTP_TIMER_NAME);
|
|
|
+}
|
|
|
+
|
|
|
+void gem_ptp_remove(struct net_device *ndev)
|
|
|
+{
|
|
|
+ struct macb *bp = netdev_priv(ndev);
|
|
|
+
|
|
|
+ if (bp->ptp_clock)
|
|
|
+ ptp_clock_unregister(bp->ptp_clock);
|
|
|
+
|
|
|
+ gem_ptp_clear_timer(bp);
|
|
|
+
|
|
|
+ dev_info(&bp->pdev->dev, "%s ptp clock unregistered.\n",
|
|
|
+ GEM_PTP_TIMER_NAME);
|
|
|
+}
|
|
|
+
|
|
|
+static int gem_ptp_set_ts_mode(struct macb *bp,
|
|
|
+ enum macb_bd_control tx_bd_control,
|
|
|
+ enum macb_bd_control rx_bd_control)
|
|
|
+{
|
|
|
+ gem_writel(bp, TXBDCTRL, GEM_BF(TXTSMODE, tx_bd_control));
|
|
|
+ gem_writel(bp, RXBDCTRL, GEM_BF(RXTSMODE, rx_bd_control));
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+int gem_get_hwtst(struct net_device *dev, struct ifreq *rq)
|
|
|
+{
|
|
|
+ struct hwtstamp_config *tstamp_config;
|
|
|
+ struct macb *bp = netdev_priv(dev);
|
|
|
+
|
|
|
+ tstamp_config = &bp->tstamp_config;
|
|
|
+ if ((bp->hw_dma_cap & HW_DMA_CAP_PTP) == 0)
|
|
|
+ return -EOPNOTSUPP;
|
|
|
+
|
|
|
+ if (copy_to_user(rq->ifr_data, tstamp_config, sizeof(*tstamp_config)))
|
|
|
+ return -EFAULT;
|
|
|
+ else
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static int gem_ptp_set_one_step_sync(struct macb *bp, u8 enable)
|
|
|
+{
|
|
|
+ u32 reg_val;
|
|
|
+
|
|
|
+ reg_val = macb_readl(bp, NCR);
|
|
|
+
|
|
|
+ if (enable)
|
|
|
+ macb_writel(bp, NCR, reg_val | MACB_BIT(OSSMODE));
|
|
|
+ else
|
|
|
+ macb_writel(bp, NCR, reg_val & ~MACB_BIT(OSSMODE));
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+int gem_set_hwtst(struct net_device *dev, struct ifreq *ifr, int cmd)
|
|
|
+{
|
|
|
+ enum macb_bd_control tx_bd_control = TSTAMP_DISABLED;
|
|
|
+ enum macb_bd_control rx_bd_control = TSTAMP_DISABLED;
|
|
|
+ struct hwtstamp_config *tstamp_config;
|
|
|
+ struct macb *bp = netdev_priv(dev);
|
|
|
+ u32 regval;
|
|
|
+
|
|
|
+ tstamp_config = &bp->tstamp_config;
|
|
|
+ if ((bp->hw_dma_cap & HW_DMA_CAP_PTP) == 0)
|
|
|
+ return -EOPNOTSUPP;
|
|
|
+
|
|
|
+ if (copy_from_user(tstamp_config, ifr->ifr_data,
|
|
|
+ sizeof(*tstamp_config)))
|
|
|
+ return -EFAULT;
|
|
|
+
|
|
|
+ /* reserved for future extensions */
|
|
|
+ if (tstamp_config->flags)
|
|
|
+ return -EINVAL;
|
|
|
+
|
|
|
+ switch (tstamp_config->tx_type) {
|
|
|
+ case HWTSTAMP_TX_OFF:
|
|
|
+ break;
|
|
|
+ case HWTSTAMP_TX_ONESTEP_SYNC:
|
|
|
+ if (gem_ptp_set_one_step_sync(bp, 1) != 0)
|
|
|
+ return -ERANGE;
|
|
|
+ case HWTSTAMP_TX_ON:
|
|
|
+ tx_bd_control = TSTAMP_ALL_FRAMES;
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ return -ERANGE;
|
|
|
+ }
|
|
|
+
|
|
|
+ switch (tstamp_config->rx_filter) {
|
|
|
+ case HWTSTAMP_FILTER_NONE:
|
|
|
+ break;
|
|
|
+ case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
|
|
|
+ break;
|
|
|
+ case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
|
|
|
+ break;
|
|
|
+ case HWTSTAMP_FILTER_PTP_V2_EVENT:
|
|
|
+ case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
|
|
|
+ case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
|
|
|
+ case HWTSTAMP_FILTER_PTP_V2_SYNC:
|
|
|
+ case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
|
|
|
+ case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
|
|
|
+ case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
|
|
|
+ case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
|
|
|
+ case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
|
|
|
+ rx_bd_control = TSTAMP_ALL_PTP_FRAMES;
|
|
|
+ tstamp_config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
|
|
|
+ regval = macb_readl(bp, NCR);
|
|
|
+ macb_writel(bp, NCR, (regval | MACB_BIT(SRTSM)));
|
|
|
+ break;
|
|
|
+ case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
|
|
|
+ case HWTSTAMP_FILTER_ALL:
|
|
|
+ rx_bd_control = TSTAMP_ALL_FRAMES;
|
|
|
+ tstamp_config->rx_filter = HWTSTAMP_FILTER_ALL;
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ tstamp_config->rx_filter = HWTSTAMP_FILTER_NONE;
|
|
|
+ return -ERANGE;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (gem_ptp_set_ts_mode(bp, tx_bd_control, rx_bd_control) != 0)
|
|
|
+ return -ERANGE;
|
|
|
+
|
|
|
+ if (copy_to_user(ifr->ifr_data, tstamp_config, sizeof(*tstamp_config)))
|
|
|
+ return -EFAULT;
|
|
|
+ else
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
Rafal Ozieblo