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@@ -2819,8 +2819,9 @@ static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
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* i40e_enable_misc_int_causes - enable the non-queue interrupts
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* @hw: ptr to the hardware info
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**/
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-static void i40e_enable_misc_int_causes(struct i40e_hw *hw)
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+static void i40e_enable_misc_int_causes(struct i40e_pf *pf)
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{
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+ struct i40e_hw *hw = &pf->hw;
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u32 val;
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/* clear things first */
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@@ -2832,11 +2833,13 @@ static void i40e_enable_misc_int_causes(struct i40e_hw *hw)
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I40E_PFINT_ICR0_ENA_GRST_MASK |
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I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
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I40E_PFINT_ICR0_ENA_GPIO_MASK |
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- I40E_PFINT_ICR0_ENA_TIMESYNC_MASK |
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I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
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I40E_PFINT_ICR0_ENA_VFLR_MASK |
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I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
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+ if (pf->flags & I40E_FLAG_PTP)
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+ val |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
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+
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wr32(hw, I40E_PFINT_ICR0_ENA, val);
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/* SW_ITR_IDX = 0, but don't change INTENA */
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@@ -2866,7 +2869,7 @@ static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
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q_vector->tx.latency_range = I40E_LOW_LATENCY;
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wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
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- i40e_enable_misc_int_causes(hw);
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+ i40e_enable_misc_int_causes(pf);
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/* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
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wr32(hw, I40E_PFINT_LNKLST0, 0);
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@@ -7137,7 +7140,7 @@ static int i40e_setup_misc_vector(struct i40e_pf *pf)
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}
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}
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- i40e_enable_misc_int_causes(hw);
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+ i40e_enable_misc_int_causes(pf);
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/* associate no queues to the misc vector */
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wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
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