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@@ -4800,8 +4800,7 @@ static void intel_post_plane_update(struct intel_crtc *crtc)
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intel_frontbuffer_flip(dev, atomic->fb_bits);
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- if (atomic->disable_cxsr)
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- crtc->wm.cxsr_allowed = true;
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+ crtc->wm.cxsr_allowed = true;
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if (crtc->atomic.update_wm_post)
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intel_update_watermarks(&crtc->base);
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@@ -4820,6 +4819,8 @@ static void intel_pre_plane_update(struct intel_crtc *crtc)
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
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+ struct intel_crtc_state *pipe_config =
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+ to_intel_crtc_state(crtc->base.state);
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if (atomic->disable_fbc)
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intel_fbc_deactivate(crtc);
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@@ -4830,7 +4831,7 @@ static void intel_pre_plane_update(struct intel_crtc *crtc)
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if (atomic->pre_disable_primary)
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intel_pre_disable_primary(&crtc->base);
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- if (atomic->disable_cxsr) {
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+ if (pipe_config->disable_cxsr) {
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crtc->wm.cxsr_allowed = false;
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intel_set_memory_cxsr(dev_priv, false);
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}
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@@ -11720,6 +11721,7 @@ static bool needs_scaling(struct intel_plane_state *state)
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int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
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struct drm_plane_state *plane_state)
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{
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+ struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
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struct drm_crtc *crtc = crtc_state->crtc;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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struct drm_plane *plane = plane_state->plane;
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@@ -11770,7 +11772,7 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
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intel_crtc->atomic.update_wm_pre = true;
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/* must disable cxsr around plane enable/disable */
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if (plane->type != DRM_PLANE_TYPE_CURSOR) {
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- intel_crtc->atomic.disable_cxsr = true;
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+ pipe_config->disable_cxsr = true;
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/* to potentially re-enable cxsr */
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intel_crtc->atomic.wait_vblank = true;
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intel_crtc->atomic.update_wm_post = true;
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@@ -11781,7 +11783,7 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
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if (plane->type != DRM_PLANE_TYPE_CURSOR) {
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if (is_crtc_enabled)
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intel_crtc->atomic.wait_vblank = true;
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- intel_crtc->atomic.disable_cxsr = true;
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+ pipe_config->disable_cxsr = true;
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}
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} else if (intel_wm_need_update(plane, plane_state)) {
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intel_crtc->atomic.update_wm_pre = true;
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