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@@ -293,7 +293,7 @@ void init_cache_modes(void)
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* pat_init - Initialize PAT MSR and PAT table
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*
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* This function initializes PAT MSR and PAT table with an OS-defined value
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- * to enable additional cache attributes, WC and WT.
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+ * to enable additional cache attributes, WC, WT and WP.
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*
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* This function must be called on all CPUs using the specific sequence of
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* operations defined in Intel SDM. mtrr_rendezvous_handler() provides this
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@@ -352,7 +352,7 @@ void pat_init(void)
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* 010 2 UC-: _PAGE_CACHE_MODE_UC_MINUS
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* 011 3 UC : _PAGE_CACHE_MODE_UC
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* 100 4 WB : Reserved
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- * 101 5 WC : Reserved
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+ * 101 5 WP : _PAGE_CACHE_MODE_WP
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* 110 6 UC-: Reserved
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* 111 7 WT : _PAGE_CACHE_MODE_WT
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*
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@@ -360,7 +360,7 @@ void pat_init(void)
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* corresponding types in the presence of PAT errata.
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*/
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pat = PAT(0, WB) | PAT(1, WC) | PAT(2, UC_MINUS) | PAT(3, UC) |
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- PAT(4, WB) | PAT(5, WC) | PAT(6, UC_MINUS) | PAT(7, WT);
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+ PAT(4, WB) | PAT(5, WP) | PAT(6, UC_MINUS) | PAT(7, WT);
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}
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if (!boot_cpu_done) {
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