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@@ -256,8 +256,11 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
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tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
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tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
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I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
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I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
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- if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
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- 100)) {
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+ if (intel_wait_for_register(dev_priv,
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+ SBI_CTL_STAT,
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+ SBI_BUSY | SBI_RESPONSE_FAIL,
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+ 0,
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+ 100)) {
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DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
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DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
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return;
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return;
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}
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}
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