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@@ -153,8 +153,8 @@ static inline void dmar_writeq(void __iomem *addr, u64 val)
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#define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60)
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#define DMA_TLB_DSI_FLUSH (((u64)2) << 60)
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#define DMA_TLB_PSI_FLUSH (((u64)3) << 60)
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-#define DMA_TLB_IIRG(type) ((type >> 60) & 7)
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-#define DMA_TLB_IAIG(val) (((val) >> 57) & 7)
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+#define DMA_TLB_IIRG(type) ((type >> 60) & 3)
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+#define DMA_TLB_IAIG(val) (((val) >> 57) & 3)
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#define DMA_TLB_READ_DRAIN (((u64)1) << 49)
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#define DMA_TLB_WRITE_DRAIN (((u64)1) << 48)
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#define DMA_TLB_DID(id) (((u64)((id) & 0xffff)) << 32)
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@@ -164,9 +164,9 @@ static inline void dmar_writeq(void __iomem *addr, u64 val)
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/* INVALID_DESC */
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#define DMA_CCMD_INVL_GRANU_OFFSET 61
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-#define DMA_ID_TLB_GLOBAL_FLUSH (((u64)1) << 3)
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-#define DMA_ID_TLB_DSI_FLUSH (((u64)2) << 3)
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-#define DMA_ID_TLB_PSI_FLUSH (((u64)3) << 3)
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+#define DMA_ID_TLB_GLOBAL_FLUSH (((u64)1) << 4)
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+#define DMA_ID_TLB_DSI_FLUSH (((u64)2) << 4)
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+#define DMA_ID_TLB_PSI_FLUSH (((u64)3) << 4)
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#define DMA_ID_TLB_READ_DRAIN (((u64)1) << 7)
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#define DMA_ID_TLB_WRITE_DRAIN (((u64)1) << 6)
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#define DMA_ID_TLB_DID(id) (((u64)((id & 0xffff) << 16)))
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@@ -316,8 +316,8 @@ enum {
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#define QI_DEV_EIOTLB_SIZE (((u64)1) << 11)
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#define QI_DEV_EIOTLB_GLOB(g) ((u64)g)
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#define QI_DEV_EIOTLB_PASID(p) (((u64)p) << 32)
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-#define QI_DEV_EIOTLB_SID(sid) ((u64)((sid) & 0xffff) << 32)
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-#define QI_DEV_EIOTLB_QDEP(qd) (((qd) & 0x1f) << 16)
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+#define QI_DEV_EIOTLB_SID(sid) ((u64)((sid) & 0xffff) << 16)
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+#define QI_DEV_EIOTLB_QDEP(qd) ((u64)((qd) & 0x1f) << 4)
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#define QI_DEV_EIOTLB_MAX_INVS 32
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#define QI_PGRP_IDX(idx) (((u64)(idx)) << 55)
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CQ Tang