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@@ -39,7 +39,7 @@ struct hpc3_pbus_dmacregs {
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volatile u32 pbdma_dptr; /* pbus dma channel desc ptr */
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volatile u32 pbdma_dptr; /* pbus dma channel desc ptr */
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u32 _unused0[0x1000/4 - 2]; /* padding */
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u32 _unused0[0x1000/4 - 2]; /* padding */
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volatile u32 pbdma_ctrl; /* pbus dma channel control register has
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volatile u32 pbdma_ctrl; /* pbus dma channel control register has
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- * copletely different meaning for read
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+ * completely different meaning for read
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* compared with write */
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* compared with write */
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/* read */
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/* read */
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#define HPC3_PDMACTRL_INT 0x00000001 /* interrupt (cleared after read) */
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#define HPC3_PDMACTRL_INT 0x00000001 /* interrupt (cleared after read) */
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