Now that Keystone PCIe controller supports error interrupt handling add interrupt property to PCI controller DT bindings to enable error interrupt handling. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
@@ -104,6 +104,8 @@
num-lanes = <2>;
bus-range = <0x00 0xff>;
+ /* error interrupt */
+ interrupts = <GIC_SPI 385 IRQ_TYPE_EDGE_RISING>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc1 0>, /* INT A */
@@ -302,6 +302,8 @@
+ interrupts = <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>;
interrupt-map = <0 0 0 1 &pcie_intc0 0>, /* INT A */