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@@ -23,6 +23,7 @@
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#include <linux/io.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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+#include <linux/clk.h>
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/*
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* This driver uses two configurable hardware resources that live in the
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@@ -61,8 +62,6 @@
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#define AT91_RTT_ALMS (1 << 0) /* Real-time Alarm Status */
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#define AT91_RTT_RTTINC (1 << 1) /* Real-time Timer Increment */
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-#define AT91_SLOW_CLOCK 32768
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-
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/*
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* We store ALARM_DISABLED in ALMV to record that no alarm is set.
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* It's also the reset value for that field.
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@@ -77,6 +76,7 @@ struct sam9_rtc {
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struct regmap *gpbr;
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unsigned int gpbr_offset;
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int irq;
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+ struct clk *sclk;
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};
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#define rtt_readl(rtc, field) \
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@@ -328,6 +328,7 @@ static int at91_rtc_probe(struct platform_device *pdev)
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struct sam9_rtc *rtc;
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int ret, irq;
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u32 mr;
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+ unsigned int sclk_rate;
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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@@ -385,11 +386,27 @@ static int at91_rtc_probe(struct platform_device *pdev)
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return -ENOMEM;
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}
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+ rtc->sclk = devm_clk_get(&pdev->dev, NULL);
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+ if (IS_ERR(rtc->sclk))
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+ return PTR_ERR(rtc->sclk);
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+
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+ sclk_rate = clk_get_rate(rtc->sclk);
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+ if (!sclk_rate || sclk_rate > AT91_RTT_RTPRES) {
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+ dev_err(&pdev->dev, "Invalid slow clock rate\n");
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+ return -EINVAL;
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+ }
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+
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+ ret = clk_prepare_enable(rtc->sclk);
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+ if (ret) {
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+ dev_err(&pdev->dev, "Could not enable slow clock\n");
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+ return ret;
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+ }
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+
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mr = rtt_readl(rtc, MR);
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/* unless RTT is counting at 1 Hz, re-initialize it */
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- if ((mr & AT91_RTT_RTPRES) != AT91_SLOW_CLOCK) {
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- mr = AT91_RTT_RTTRST | (AT91_SLOW_CLOCK & AT91_RTT_RTPRES);
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+ if ((mr & AT91_RTT_RTPRES) != sclk_rate) {
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+ mr = AT91_RTT_RTTRST | (sclk_rate & AT91_RTT_RTPRES);
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gpbr_writel(rtc, 0);
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}
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@@ -434,6 +451,9 @@ static int at91_rtc_remove(struct platform_device *pdev)
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/* disable all interrupts */
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rtt_writel(rtc, MR, mr & ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN));
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+ if (!IS_ERR(rtc->sclk))
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+ clk_disable_unprepare(rtc->sclk);
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+
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return 0;
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}
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