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@@ -28,4 +28,63 @@ void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val);
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#define I40E_XDP_TX BIT(1)
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#define I40E_XDP_REDIR BIT(2)
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+/**
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+ * build_ctob - Builds the Tx descriptor (cmd, offset and type) qword
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+ **/
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+static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
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+ u32 td_tag)
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+{
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+ return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
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+ ((u64)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
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+ ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
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+ ((u64)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
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+ ((u64)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
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+}
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+
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+/**
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+ * i40e_update_tx_stats - Update the egress statistics for the Tx ring
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+ * @tx_ring: Tx ring to update
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+ * @total_packet: total packets sent
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+ * @total_bytes: total bytes sent
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+ **/
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+static inline void i40e_update_tx_stats(struct i40e_ring *tx_ring,
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+ unsigned int total_packets,
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+ unsigned int total_bytes)
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+{
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+ u64_stats_update_begin(&tx_ring->syncp);
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+ tx_ring->stats.bytes += total_bytes;
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+ tx_ring->stats.packets += total_packets;
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+ u64_stats_update_end(&tx_ring->syncp);
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+ tx_ring->q_vector->tx.total_bytes += total_bytes;
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+ tx_ring->q_vector->tx.total_packets += total_packets;
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+}
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+
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+#define WB_STRIDE 4
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+
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+/**
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+ * i40e_arm_wb - (Possibly) arms Tx write-back
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+ * @tx_ring: Tx ring to update
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+ * @vsi: the VSI
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+ * @budget: the NAPI budget left
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+ **/
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+static inline void i40e_arm_wb(struct i40e_ring *tx_ring,
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+ struct i40e_vsi *vsi,
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+ int budget)
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+{
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+ if (tx_ring->flags & I40E_TXR_FLAGS_WB_ON_ITR) {
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+ /* check to see if there are < 4 descriptors
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+ * waiting to be written back, then kick the hardware to force
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+ * them to be written back in case we stay in NAPI.
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+ * In this mode on X722 we do not enable Interrupt.
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+ */
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+ unsigned int j = i40e_get_tx_pending(tx_ring, false);
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+
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+ if (budget &&
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+ ((j / WB_STRIDE) == 0) && j > 0 &&
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+ !test_bit(__I40E_VSI_DOWN, vsi->state) &&
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+ (I40E_DESC_UNUSED(tx_ring) != tx_ring->count))
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+ tx_ring->arm_wb = true;
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+ }
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+}
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+
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#endif /* I40E_TXRX_COMMON_ */
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