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@@ -124,16 +124,15 @@ static int hdmi_pll_config(struct hdmi_pll_data *pll)
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r = FLD_MOD(r, 0x0, 14, 14); /* PHY_CLKINEN de-assert during locking */
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r = FLD_MOD(r, fmt->refsel, 22, 21); /* REFSEL */
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- if (fmt->dcofreq) {
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- /* divider programming for frequency beyond 1000Mhz */
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- REG_FLD_MOD(pll->base, PLLCTRL_CFG3, fmt->regsd, 17, 10);
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+ if (fmt->dcofreq)
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r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */
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- } else {
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+ else
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r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */
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- }
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hdmi_write_reg(pll->base, PLLCTRL_CFG2, r);
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+ REG_FLD_MOD(pll->base, PLLCTRL_CFG3, fmt->regsd, 17, 10);
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+
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r = hdmi_read_reg(pll->base, PLLCTRL_CFG4);
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r = FLD_MOD(r, fmt->regm2, 24, 18);
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r = FLD_MOD(r, fmt->regmf, 17, 0);
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@@ -144,8 +143,8 @@ static int hdmi_pll_config(struct hdmi_pll_data *pll)
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/* wait for bit change */
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if (hdmi_wait_for_bit_change(pll->base, PLLCTRL_PLL_GO,
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- 0, 0, 1) != 1) {
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- DSSERR("PLL GO bit not set\n");
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+ 0, 0, 0) != 0) {
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+ DSSERR("PLL GO bit not clearing\n");
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return -ETIMEDOUT;
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}
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