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@@ -82,9 +82,11 @@
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compatible = "arm,cortex-a15";
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reg = <0>;
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- operating-points-v2 = <&cpu0_opp_table>;
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- ti,syscon-efuse = <&scm_wkup 0x20c 0xf80000 19>;
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- ti,syscon-rev = <&scm_wkup 0x204>;
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+ operating-points = <
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+ /* kHz uV */
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+ 1000000 1060000
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+ 1176000 1160000
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+ >;
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clocks = <&dpll_mpu_ck>;
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clock-names = "cpu";
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@@ -98,24 +100,6 @@
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};
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};
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- cpu0_opp_table: opp_table0 {
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- compatible = "operating-points-v2";
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- opp-shared;
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-
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- opp_nom@1000000000 {
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- opp-hz = /bits/ 64 <1000000000>;
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- opp-microvolt = <1060000 850000 1150000>;
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- opp-supported-hw = <0xFF 0x01>;
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- opp-suspend;
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- };
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-
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- opp_od@1176000000 {
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- opp-hz = /bits/ 64 <1176000000>;
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- opp-microvolt = <1160000 885000 1160000>;
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- opp-supported-hw = <0xFF 0x02>;
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- };
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- };
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-
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/*
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* The soc node represents the soc top level view. It is used for IPs
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* that are not memory mapped in the MPU view or for the MPU itself.
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