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@@ -8,6 +8,7 @@
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* Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
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* Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
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* Copyright(c) 2016 - 2017 Intel Deutschland GmbH
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+ * Copyright(c) 2018 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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@@ -35,6 +36,7 @@
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* Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
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* Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
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* Copyright(c) 2016 - 2017 Intel Deutschland GmbH
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+ * Copyright(c) 2018 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@@ -179,7 +181,8 @@ out:
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static void iwl_trans_pcie_sw_reset(struct iwl_trans *trans)
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{
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/* Reset entire device - do controller reset (results in SHRD_HW_RST) */
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- iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
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+ iwl_set_bit(trans, trans->cfg->csr->addr_sw_reset,
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+ BIT(trans->cfg->csr->flag_sw_reset));
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usleep_range(5000, 6000);
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}
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@@ -372,7 +375,8 @@ static int iwl_pcie_apm_init(struct iwl_trans *trans)
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* Set "initialization complete" bit to move adapter from
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* D0U* --> D0A* (powered-up active) state.
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*/
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- iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
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+ iwl_set_bit(trans, CSR_GP_CNTRL,
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+ BIT(trans->cfg->csr->flag_init_done));
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/*
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* Wait for clock stabilization; once stabilized, access to
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@@ -380,8 +384,9 @@ static int iwl_pcie_apm_init(struct iwl_trans *trans)
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* and accesses to uCode SRAM.
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*/
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ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
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- CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
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- CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
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+ BIT(trans->cfg->csr->flag_mac_clock_ready),
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+ BIT(trans->cfg->csr->flag_mac_clock_ready),
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+ 25000);
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if (ret < 0) {
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IWL_ERR(trans, "Failed to init the card\n");
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return ret;
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@@ -459,15 +464,16 @@ static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
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* Set "initialization complete" bit to move adapter from
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* D0U* --> D0A* (powered-up active) state.
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*/
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- iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
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+ iwl_set_bit(trans, CSR_GP_CNTRL,
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+ BIT(trans->cfg->csr->flag_init_done));
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/*
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* Wait for clock stabilization; once stabilized, access to
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* device-internal resources is possible.
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*/
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ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
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- CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
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- CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
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+ BIT(trans->cfg->csr->flag_mac_clock_ready),
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+ BIT(trans->cfg->csr->flag_mac_clock_ready),
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25000);
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if (WARN_ON(ret < 0)) {
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IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
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@@ -519,7 +525,7 @@ static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
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* D0A* (powered-up Active) --> D0U* (Uninitialized) state.
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*/
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iwl_clear_bit(trans, CSR_GP_CNTRL,
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- CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
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+ BIT(trans->cfg->csr->flag_init_done));
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/* Activates XTAL resources monitor */
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__iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
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@@ -541,11 +547,12 @@ void iwl_pcie_apm_stop_master(struct iwl_trans *trans)
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int ret;
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/* stop device's busmaster DMA activity */
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- iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
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+ iwl_set_bit(trans, trans->cfg->csr->addr_sw_reset,
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+ BIT(trans->cfg->csr->flag_stop_master));
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- ret = iwl_poll_bit(trans, CSR_RESET,
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- CSR_RESET_REG_FLAG_MASTER_DISABLED,
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- CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
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+ ret = iwl_poll_bit(trans, trans->cfg->csr->addr_sw_reset,
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+ BIT(trans->cfg->csr->flag_master_dis),
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+ BIT(trans->cfg->csr->flag_master_dis), 100);
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if (ret < 0)
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IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
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@@ -594,7 +601,7 @@ static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
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* D0A* (powered-up Active) --> D0U* (Uninitialized) state.
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*/
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iwl_clear_bit(trans, CSR_GP_CNTRL,
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- CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
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+ BIT(trans->cfg->csr->flag_init_done));
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}
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static int iwl_pcie_nic_init(struct iwl_trans *trans)
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@@ -1267,7 +1274,7 @@ static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
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/* Make sure (redundant) we've released our request to stay awake */
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iwl_clear_bit(trans, CSR_GP_CNTRL,
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- CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
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+ BIT(trans->cfg->csr->flag_mac_access_req));
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/* Stop the device, and put it in low power state */
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iwl_pcie_apm_stop(trans, false);
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@@ -1497,9 +1504,9 @@ static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
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iwl_pcie_synchronize_irqs(trans);
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iwl_clear_bit(trans, CSR_GP_CNTRL,
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- CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
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+ BIT(trans->cfg->csr->flag_mac_access_req));
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iwl_clear_bit(trans, CSR_GP_CNTRL,
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- CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
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+ BIT(trans->cfg->csr->flag_init_done));
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iwl_pcie_enable_rx_wake(trans, false);
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@@ -1543,15 +1550,17 @@ static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
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iwl_pcie_reset_ict(trans);
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iwl_enable_interrupts(trans);
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- iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
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- iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
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+ iwl_set_bit(trans, CSR_GP_CNTRL,
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+ BIT(trans->cfg->csr->flag_mac_access_req));
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+ iwl_set_bit(trans, CSR_GP_CNTRL,
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+ BIT(trans->cfg->csr->flag_init_done));
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if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
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udelay(2);
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ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
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- CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
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- CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
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+ BIT(trans->cfg->csr->flag_mac_clock_ready),
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+ BIT(trans->cfg->csr->flag_mac_clock_ready),
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25000);
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if (ret < 0) {
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IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
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@@ -1562,7 +1571,7 @@ static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
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if (!reset) {
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iwl_clear_bit(trans, CSR_GP_CNTRL,
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- CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
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+ BIT(trans->cfg->csr->flag_mac_access_req));
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} else {
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iwl_trans_pcie_tx_reset(trans);
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@@ -1939,7 +1948,7 @@ static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
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/* this bit wakes up the NIC */
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__iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
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- CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
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+ BIT(trans->cfg->csr->flag_mac_access_req));
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if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
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udelay(2);
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@@ -1964,8 +1973,8 @@ static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
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* and do not save/restore SRAM when power cycling.
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*/
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ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
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- CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
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- (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
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+ BIT(trans->cfg->csr->flag_val_mac_access_en),
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+ (BIT(trans->cfg->csr->flag_mac_clock_ready) |
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CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
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if (unlikely(ret < 0)) {
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iwl_trans_pcie_dump_regs(trans);
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@@ -2003,7 +2012,7 @@ static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
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goto out;
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__iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
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- CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
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+ BIT(trans->cfg->csr->flag_mac_access_req));
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/*
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* Above we read the CSR_GP_CNTRL register, which will flush
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* any previous writes, but we need the write that clears the
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@@ -3232,12 +3241,12 @@ struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
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* id located at the AUX bus MISC address space.
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*/
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iwl_set_bit(trans, CSR_GP_CNTRL,
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- CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
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+ BIT(trans->cfg->csr->flag_init_done));
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udelay(2);
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ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
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- CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
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- CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
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+ BIT(trans->cfg->csr->flag_mac_clock_ready),
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+ BIT(trans->cfg->csr->flag_mac_clock_ready),
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25000);
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if (ret < 0) {
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IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
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