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@@ -253,10 +253,6 @@
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#define MVPP2_SRC_ADDR_HIGH 0x28
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#define MVPP2_PHY_AN_CFG0_REG 0x34
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#define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7)
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-#define MVPP2_MIB_COUNTERS_BASE(port) (0x1000 + ((port) >> 1) * \
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- 0x400 + (port) * 0x400)
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-#define MVPP2_MIB_LATE_COLLISION 0x7c
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-#define MVPP2_ISR_SUM_MASK_REG 0x220c
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#define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c
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#define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27
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