|
@@ -669,10 +669,8 @@ tda998x_configure_audio(struct tda998x_priv *priv,
|
|
|
}
|
|
|
|
|
|
reg_write(priv, REG_AIP_CLKSEL, clksel_aip);
|
|
|
- reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT);
|
|
|
-
|
|
|
- /* Enable automatic CTS generation */
|
|
|
- reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_ACR_MAN);
|
|
|
+ reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT |
|
|
|
+ AIP_CNTRL_0_ACR_MAN); /* auto CTS */
|
|
|
reg_write(priv, REG_CTS_N, cts_n);
|
|
|
|
|
|
/*
|
|
@@ -908,10 +906,10 @@ tda998x_encoder_mode_set(struct drm_encoder *encoder,
|
|
|
reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
|
|
|
reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) |
|
|
|
VIP_CNTRL_4_BLC(0));
|
|
|
- reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR);
|
|
|
|
|
|
reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ);
|
|
|
- reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_DE);
|
|
|
+ reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR |
|
|
|
+ PLL_SERIAL_3_SRL_DE);
|
|
|
reg_write(priv, REG_SERIALIZER, 0);
|
|
|
reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0));
|
|
|
|
|
@@ -931,8 +929,6 @@ tda998x_encoder_mode_set(struct drm_encoder *encoder,
|
|
|
/* set BIAS tmds value: */
|
|
|
reg_write(priv, REG_ANA_GENERAL, 0x09);
|
|
|
|
|
|
- reg_write(priv, REG_TBG_CNTRL_0, 0);
|
|
|
-
|
|
|
/*
|
|
|
* Sync on rising HSYNC/VSYNC
|
|
|
*/
|