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@@ -2694,7 +2694,7 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
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u32 reg = DSPCNTR(plane);
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u32 reg = DSPCNTR(plane);
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int pixel_size;
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int pixel_size;
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- if (!intel_crtc->primary_enabled) {
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+ if (!intel_crtc->primary_enabled || !fb) {
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I915_WRITE(reg, 0);
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I915_WRITE(reg, 0);
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if (INTEL_INFO(dev)->gen >= 4)
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if (INTEL_INFO(dev)->gen >= 4)
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I915_WRITE(DSPSURF(plane), 0);
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I915_WRITE(DSPSURF(plane), 0);
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@@ -2823,7 +2823,7 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
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u32 reg = DSPCNTR(plane);
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u32 reg = DSPCNTR(plane);
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int pixel_size;
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int pixel_size;
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- if (!intel_crtc->primary_enabled) {
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+ if (!intel_crtc->primary_enabled || !fb) {
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I915_WRITE(reg, 0);
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I915_WRITE(reg, 0);
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I915_WRITE(DSPSURF(plane), 0);
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I915_WRITE(DSPSURF(plane), 0);
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POSTING_READ(reg);
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POSTING_READ(reg);
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@@ -3102,7 +3102,7 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
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plane = crtc->primary;
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plane = crtc->primary;
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plane_state = to_intel_plane_state(plane->state);
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plane_state = to_intel_plane_state(plane->state);
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- if (!intel_crtc->primary_enabled) {
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+ if (!intel_crtc->primary_enabled || !fb) {
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I915_WRITE(PLANE_CTL(pipe, 0), 0);
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I915_WRITE(PLANE_CTL(pipe, 0), 0);
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I915_WRITE(PLANE_SURF(pipe, 0), 0);
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I915_WRITE(PLANE_SURF(pipe, 0), 0);
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POSTING_READ(PLANE_CTL(pipe, 0));
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POSTING_READ(PLANE_CTL(pipe, 0));
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@@ -13378,6 +13378,20 @@ intel_commit_primary_plane(struct drm_plane *plane,
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}
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}
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}
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}
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+static void
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+intel_disable_primary_plane(struct drm_plane *plane,
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+ struct drm_crtc *crtc,
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+ bool force)
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+{
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+ struct drm_device *dev = plane->dev;
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+ struct drm_i915_private *dev_priv = dev->dev_private;
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+
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+ if (!force)
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+ to_intel_crtc(crtc)->primary_enabled = false;
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+
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+ dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
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+}
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+
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static void intel_begin_crtc_commit(struct drm_crtc *crtc)
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static void intel_begin_crtc_commit(struct drm_crtc *crtc)
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{
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{
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struct drm_device *dev = crtc->dev;
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struct drm_device *dev = crtc->dev;
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@@ -13522,6 +13536,7 @@ static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
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primary->plane = pipe;
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primary->plane = pipe;
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primary->check_plane = intel_check_primary_plane;
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primary->check_plane = intel_check_primary_plane;
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primary->commit_plane = intel_commit_primary_plane;
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primary->commit_plane = intel_commit_primary_plane;
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+ primary->disable_plane = intel_disable_primary_plane;
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primary->ckey.flags = I915_SET_COLORKEY_NONE;
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primary->ckey.flags = I915_SET_COLORKEY_NONE;
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if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
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if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
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primary->plane = !pipe;
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primary->plane = !pipe;
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@@ -13626,6 +13641,22 @@ finish:
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return ret;
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return ret;
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}
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}
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+static void
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+intel_disable_cursor_plane(struct drm_plane *plane,
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+ struct drm_crtc *crtc,
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+ bool force)
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+{
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+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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+
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+ if (!force) {
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+ plane->fb = NULL;
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+ intel_crtc->cursor_bo = NULL;
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+ intel_crtc->cursor_addr = 0;
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+ }
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+
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+ intel_crtc_update_cursor(crtc, false);
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+}
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+
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static void
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static void
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intel_commit_cursor_plane(struct drm_plane *plane,
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intel_commit_cursor_plane(struct drm_plane *plane,
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struct intel_plane_state *state)
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struct intel_plane_state *state)
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@@ -13685,6 +13716,7 @@ static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
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state->scaler_id = -1;
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state->scaler_id = -1;
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cursor->check_plane = intel_check_cursor_plane;
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cursor->check_plane = intel_check_cursor_plane;
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cursor->commit_plane = intel_commit_cursor_plane;
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cursor->commit_plane = intel_commit_cursor_plane;
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+ cursor->disable_plane = intel_disable_cursor_plane;
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drm_universal_plane_init(dev, &cursor->base, 0,
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drm_universal_plane_init(dev, &cursor->base, 0,
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&intel_plane_funcs,
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&intel_plane_funcs,
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