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@@ -812,12 +812,10 @@ static int sd_change_phase(struct rtsx_chip *chip, u8 sample_point, u8 tune_dir)
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PHASE_NOT_RESET);
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RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, 0);
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} else {
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-#ifdef CONFIG_RTS5208_DEBUG
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rtsx_read_register(chip, SD_VP_CTL, &val);
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dev_dbg(rtsx_dev(chip), "SD_VP_CTL: 0x%x\n", val);
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rtsx_read_register(chip, SD_DCMPS_CTL, &val);
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dev_dbg(rtsx_dev(chip), "SD_DCMPS_CTL: 0x%x\n", val);
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-#endif
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if (ddr_rx) {
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RTSX_WRITE_REG(chip, SD_VP_CTL, PHASE_CHANGE,
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@@ -863,12 +861,11 @@ static int sd_change_phase(struct rtsx_chip *chip, u8 sample_point, u8 tune_dir)
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return STATUS_SUCCESS;
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Fail:
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-#ifdef CONFIG_RTS5208_DEBUG
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rtsx_read_register(chip, SD_VP_CTL, &val);
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dev_dbg(rtsx_dev(chip), "SD_VP_CTL: 0x%x\n", val);
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rtsx_read_register(chip, SD_DCMPS_CTL, &val);
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dev_dbg(rtsx_dev(chip), "SD_DCMPS_CTL: 0x%x\n", val);
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-#endif
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+
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rtsx_write_register(chip, SD_DCMPS_CTL, DCMPS_CHANGE, 0);
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rtsx_write_register(chip, SD_VP_CTL, PHASE_CHANGE, 0);
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wait_timeout(10);
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