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@@ -300,15 +300,15 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
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COMPOSITE(0, "i2s_src", mux_pll_src_cpll_gpll_p, 0,
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COMPOSITE(0, "i2s_src", mux_pll_src_cpll_gpll_p, 0,
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RK3288_CLKSEL_CON(4), 15, 1, MFLAGS, 0, 7, DFLAGS,
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RK3288_CLKSEL_CON(4), 15, 1, MFLAGS, 0, 7, DFLAGS,
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RK3288_CLKGATE_CON(4), 1, GFLAGS),
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RK3288_CLKGATE_CON(4), 1, GFLAGS),
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- COMPOSITE_FRAC(0, "i2s_frac", "i2s_src", 0,
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+ COMPOSITE_FRAC(0, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT,
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RK3288_CLKSEL_CON(8), 0,
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RK3288_CLKSEL_CON(8), 0,
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RK3288_CLKGATE_CON(4), 2, GFLAGS),
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RK3288_CLKGATE_CON(4), 2, GFLAGS),
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- MUX(0, "i2s_pre", mux_i2s_pre_p, 0,
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+ MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT,
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RK3288_CLKSEL_CON(4), 8, 2, MFLAGS),
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RK3288_CLKSEL_CON(4), 8, 2, MFLAGS),
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- COMPOSITE_NODIV(0, "i2s0_clkout", mux_i2s_clkout_p, 0,
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+ COMPOSITE_NODIV(0, "i2s0_clkout", mux_i2s_clkout_p, CLK_SET_RATE_PARENT,
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RK3288_CLKSEL_CON(4), 12, 1, MFLAGS,
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RK3288_CLKSEL_CON(4), 12, 1, MFLAGS,
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RK3288_CLKGATE_CON(4), 0, GFLAGS),
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RK3288_CLKGATE_CON(4), 0, GFLAGS),
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- GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", 0,
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+ GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", CLK_SET_RATE_PARENT,
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RK3288_CLKGATE_CON(4), 3, GFLAGS),
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RK3288_CLKGATE_CON(4), 3, GFLAGS),
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MUX(0, "spdif_src", mux_pll_src_cpll_gpll_p, 0,
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MUX(0, "spdif_src", mux_pll_src_cpll_gpll_p, 0,
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@@ -808,5 +808,7 @@ static void __init rk3288_clk_init(struct device_node *np)
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rockchip_register_softrst(np, 12, reg_base + RK3288_SOFTRST_CON(0),
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rockchip_register_softrst(np, 12, reg_base + RK3288_SOFTRST_CON(0),
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ROCKCHIP_SOFTRST_HIWORD_MASK);
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ROCKCHIP_SOFTRST_HIWORD_MASK);
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+
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+ rockchip_register_restart_notifier(RK3288_GLB_SRST_FST);
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}
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}
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CLK_OF_DECLARE(rk3288_cru, "rockchip,rk3288-cru", rk3288_clk_init);
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CLK_OF_DECLARE(rk3288_cru, "rockchip,rk3288-cru", rk3288_clk_init);
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