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@@ -247,9 +247,6 @@ static int imx6q_pcie_abort_handler(unsigned long addr,
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static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
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{
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- struct pcie_port *pp = &imx6_pcie->pp;
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- u32 val, gpr1, gpr12;
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-
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switch (imx6_pcie->variant) {
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case IMX6SX:
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
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@@ -266,33 +263,6 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
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IMX6Q_GPR1_PCIE_SW_RST);
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break;
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case IMX6Q:
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- /*
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- * If the bootloader already enabled the link we need some
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- * special handling to get the core back into a state where
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- * it is safe to touch it for configuration. As there is
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- * no dedicated reset signal wired up for MX6QDL, we need
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- * to manually force LTSSM into "detect" state before
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- * completely disabling LTSSM, which is a prerequisite for
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- * core configuration.
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- *
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- * If both LTSSM_ENABLE and REF_SSP_ENABLE are active we
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- * have a strong indication that the bootloader activated
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- * the link.
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- */
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- regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, &gpr1);
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- regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, &gpr12);
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-
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- if ((gpr1 & IMX6Q_GPR1_PCIE_REF_CLK_EN) &&
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- (gpr12 & IMX6Q_GPR12_PCIE_CTL_2)) {
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- val = dw_pcie_readl_rc(pp, PCIE_PL_PFLR);
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- val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
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- val |= PCIE_PL_PFLR_FORCE_LINK;
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- dw_pcie_writel_rc(pp, PCIE_PL_PFLR, val);
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-
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- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
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- IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
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- }
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-
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
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IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
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