|
@@ -316,12 +316,12 @@ static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer)
|
|
OMAP_TIMER_V1_SYS_STAT_OFFSET;
|
|
OMAP_TIMER_V1_SYS_STAT_OFFSET;
|
|
timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET;
|
|
timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET;
|
|
timer->irq_ena = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
|
|
timer->irq_ena = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
|
|
- timer->irq_dis = 0;
|
|
|
|
|
|
+ timer->irq_dis = NULL;
|
|
timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET;
|
|
timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET;
|
|
timer->func_base = timer->io_base;
|
|
timer->func_base = timer->io_base;
|
|
} else {
|
|
} else {
|
|
timer->revision = 2;
|
|
timer->revision = 2;
|
|
- timer->sys_stat = 0;
|
|
|
|
|
|
+ timer->sys_stat = NULL;
|
|
timer->irq_stat = timer->io_base + OMAP_TIMER_V2_IRQSTATUS;
|
|
timer->irq_stat = timer->io_base + OMAP_TIMER_V2_IRQSTATUS;
|
|
timer->irq_ena = timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET;
|
|
timer->irq_ena = timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET;
|
|
timer->irq_dis = timer->io_base + OMAP_TIMER_V2_IRQENABLE_CLR;
|
|
timer->irq_dis = timer->io_base + OMAP_TIMER_V2_IRQENABLE_CLR;
|