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@@ -922,11 +922,29 @@ void ath9k_hw_set_interrupts(struct ath_hw *ah)
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mask2 |= AR_IMR_S2_CST;
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}
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+ if (ah->config.hw_hang_checks & HW_BB_WATCHDOG) {
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+ if (ints & ATH9K_INT_BB_WATCHDOG) {
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+ mask |= AR_IMR_BCNMISC;
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+ mask2 |= AR_IMR_S2_BB_WATCHDOG;
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+ }
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+ }
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+
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ath_dbg(common, INTERRUPT, "new IMR 0x%x\n", mask);
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REG_WRITE(ah, AR_IMR, mask);
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- ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
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- AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
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- AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
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+ ah->imrs2_reg &= ~(AR_IMR_S2_TIM |
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+ AR_IMR_S2_DTIM |
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+ AR_IMR_S2_DTIMSYNC |
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+ AR_IMR_S2_CABEND |
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+ AR_IMR_S2_CABTO |
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+ AR_IMR_S2_TSFOOR |
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+ AR_IMR_S2_GTT |
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+ AR_IMR_S2_CST);
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+
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+ if (ah->config.hw_hang_checks & HW_BB_WATCHDOG) {
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+ if (ints & ATH9K_INT_BB_WATCHDOG)
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+ ah->imrs2_reg &= ~AR_IMR_S2_BB_WATCHDOG;
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+ }
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+
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ah->imrs2_reg |= mask2;
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REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
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