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@@ -35,10 +35,10 @@
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#define AD7192_REG_DATA 3 /* Data Register (RO, 24/32-bit) */
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#define AD7192_REG_ID 4 /* ID Register (RO, 8-bit) */
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#define AD7192_REG_GPOCON 5 /* GPOCON Register (RO, 8-bit) */
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-#define AD7192_REG_OFFSET 6 /* Offset Register (RW, 16-bit
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- * (AD7792)/24-bit (AD7192)) */
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-#define AD7192_REG_FULLSALE 7 /* Full-Scale Register
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- * (RW, 16-bit (AD7792)/24-bit (AD7192)) */
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+#define AD7192_REG_OFFSET 6 /* Offset Register (RW, 16-bit */
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+ /* (AD7792)/24-bit (AD7192)) */
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+#define AD7192_REG_FULLSALE 7 /* Full-Scale Register */
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+ /* (RW, 16-bit (AD7792)/24-bit (AD7192)) */
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/* Communications Register Bit Designations (AD7192_REG_COMM) */
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#define AD7192_COMM_WEN BIT(7) /* Write Enable */
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@@ -80,13 +80,13 @@
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#define AD7192_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */
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/* Mode Register: AD7192_MODE_CLKSRC options */
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-#define AD7192_CLK_EXT_MCLK1_2 0 /* External 4.92 MHz Clock connected
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- * from MCLK1 to MCLK2 */
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+#define AD7192_CLK_EXT_MCLK1_2 0 /* External 4.92 MHz Clock connected*/
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+ /* from MCLK1 to MCLK2 */
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#define AD7192_CLK_EXT_MCLK2 1 /* External Clock applied to MCLK2 */
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-#define AD7192_CLK_INT 2 /* Internal 4.92 MHz Clock not
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- * available at the MCLK2 pin */
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-#define AD7192_CLK_INT_CO 3 /* Internal 4.92 MHz Clock available
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- * at the MCLK2 pin */
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+#define AD7192_CLK_INT 2 /* Internal 4.92 MHz Clock not */
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+ /* available at the MCLK2 pin */
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+#define AD7192_CLK_INT_CO 3 /* Internal 4.92 MHz Clock available*/
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+ /* at the MCLK2 pin */
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/* Configuration Register Bit Designations (AD7192_REG_CONF) */
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