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@@ -21,6 +21,7 @@
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*******************************************************************************/
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*******************************************************************************/
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#include <linux/io.h>
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#include <linux/io.h>
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+#include <linux/iopoll.h>
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#include <linux/mii.h>
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#include <linux/mii.h>
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#include <linux/of.h>
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#include <linux/of.h>
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#include <linux/of_gpio.h>
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#include <linux/of_gpio.h>
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@@ -38,22 +39,6 @@
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#define MII_GMAC4_WRITE (1 << MII_GMAC4_GOC_SHIFT)
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#define MII_GMAC4_WRITE (1 << MII_GMAC4_GOC_SHIFT)
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#define MII_GMAC4_READ (3 << MII_GMAC4_GOC_SHIFT)
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#define MII_GMAC4_READ (3 << MII_GMAC4_GOC_SHIFT)
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-static int stmmac_mdio_busy_wait(void __iomem *ioaddr, unsigned int mii_addr)
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-{
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- unsigned long curr;
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- unsigned long finish = jiffies + 3 * HZ;
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-
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- do {
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- curr = jiffies;
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- if (readl(ioaddr + mii_addr) & MII_BUSY)
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- cpu_relax();
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- else
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- return 0;
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- } while (!time_after_eq(curr, finish));
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-
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- return -EBUSY;
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-}
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-
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/**
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/**
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* stmmac_mdio_read
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* stmmac_mdio_read
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* @bus: points to the mii_bus structure
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* @bus: points to the mii_bus structure
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@@ -70,7 +55,7 @@ static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
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struct stmmac_priv *priv = netdev_priv(ndev);
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struct stmmac_priv *priv = netdev_priv(ndev);
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unsigned int mii_address = priv->hw->mii.addr;
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unsigned int mii_address = priv->hw->mii.addr;
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unsigned int mii_data = priv->hw->mii.data;
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unsigned int mii_data = priv->hw->mii.data;
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-
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+ u32 v;
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int data;
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int data;
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u32 value = MII_BUSY;
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u32 value = MII_BUSY;
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@@ -82,12 +67,14 @@ static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
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if (priv->plat->has_gmac4)
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if (priv->plat->has_gmac4)
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value |= MII_GMAC4_READ;
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value |= MII_GMAC4_READ;
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- if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address))
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+ if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY),
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+ 100, 10000))
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return -EBUSY;
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return -EBUSY;
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writel(value, priv->ioaddr + mii_address);
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writel(value, priv->ioaddr + mii_address);
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- if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address))
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+ if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY),
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+ 100, 10000))
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return -EBUSY;
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return -EBUSY;
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/* Read the data from the MII data register */
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/* Read the data from the MII data register */
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@@ -111,7 +98,7 @@ static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg,
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struct stmmac_priv *priv = netdev_priv(ndev);
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struct stmmac_priv *priv = netdev_priv(ndev);
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unsigned int mii_address = priv->hw->mii.addr;
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unsigned int mii_address = priv->hw->mii.addr;
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unsigned int mii_data = priv->hw->mii.data;
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unsigned int mii_data = priv->hw->mii.data;
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-
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+ u32 v;
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u32 value = MII_BUSY;
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u32 value = MII_BUSY;
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value |= (phyaddr << priv->hw->mii.addr_shift)
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value |= (phyaddr << priv->hw->mii.addr_shift)
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@@ -126,7 +113,8 @@ static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg,
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value |= MII_WRITE;
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value |= MII_WRITE;
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/* Wait until any existing MII operation is complete */
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/* Wait until any existing MII operation is complete */
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- if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address))
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+ if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY),
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+ 100, 10000))
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return -EBUSY;
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return -EBUSY;
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/* Set the MII address register to write */
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/* Set the MII address register to write */
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@@ -134,7 +122,8 @@ static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg,
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writel(value, priv->ioaddr + mii_address);
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writel(value, priv->ioaddr + mii_address);
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/* Wait until any existing MII operation is complete */
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/* Wait until any existing MII operation is complete */
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- return stmmac_mdio_busy_wait(priv->ioaddr, mii_address);
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+ return readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY),
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+ 100, 10000);
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}
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}
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/**
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/**
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