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@@ -0,0 +1,1005 @@
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+/*
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+ * MIPI Display Bus Interface (DBI) LCD controller support
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+ *
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+ * Copyright 2016 Noralf Trønnes
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; either version 2 of the License, or
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+ * (at your option) any later version.
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+ */
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+
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+#include <drm/tinydrm/mipi-dbi.h>
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+#include <drm/tinydrm/tinydrm-helpers.h>
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+#include <linux/debugfs.h>
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+#include <linux/dma-buf.h>
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+#include <linux/gpio/consumer.h>
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+#include <linux/module.h>
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+#include <linux/regulator/consumer.h>
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+#include <linux/spi/spi.h>
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+#include <video/mipi_display.h>
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+
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+#define MIPI_DBI_MAX_SPI_READ_SPEED 2000000 /* 2MHz */
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+
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+#define DCS_POWER_MODE_DISPLAY BIT(2)
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+#define DCS_POWER_MODE_DISPLAY_NORMAL_MODE BIT(3)
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+#define DCS_POWER_MODE_SLEEP_MODE BIT(4)
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+#define DCS_POWER_MODE_PARTIAL_MODE BIT(5)
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+#define DCS_POWER_MODE_IDLE_MODE BIT(6)
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+#define DCS_POWER_MODE_RESERVED_MASK (BIT(0) | BIT(1) | BIT(7))
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+
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+/**
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+ * DOC: overview
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+ *
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+ * This library provides helpers for MIPI Display Bus Interface (DBI)
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+ * compatible display controllers.
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+ *
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+ * Many controllers for tiny lcd displays are MIPI compliant and can use this
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+ * library. If a controller uses registers 0x2A and 0x2B to set the area to
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+ * update and uses register 0x2C to write to frame memory, it is most likely
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+ * MIPI compliant.
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+ *
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+ * Only MIPI Type 1 displays are supported since a full frame memory is needed.
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+ *
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+ * There are 3 MIPI DBI implementation types:
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+ *
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+ * A. Motorola 6800 type parallel bus
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+ *
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+ * B. Intel 8080 type parallel bus
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+ *
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+ * C. SPI type with 3 options:
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+ *
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+ * 1. 9-bit with the Data/Command signal as the ninth bit
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+ * 2. Same as above except it's sent as 16 bits
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+ * 3. 8-bit with the Data/Command signal as a separate D/CX pin
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+ *
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+ * Currently mipi_dbi only supports Type C options 1 and 3 with
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+ * mipi_dbi_spi_init().
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+ */
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+
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+#define MIPI_DBI_DEBUG_COMMAND(cmd, data, len) \
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+({ \
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+ if (!len) \
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+ DRM_DEBUG_DRIVER("cmd=%02x\n", cmd); \
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+ else if (len <= 32) \
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+ DRM_DEBUG_DRIVER("cmd=%02x, par=%*ph\n", cmd, len, data); \
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+ else \
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+ DRM_DEBUG_DRIVER("cmd=%02x, len=%zu\n", cmd, len); \
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+})
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+
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+static const u8 mipi_dbi_dcs_read_commands[] = {
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+ MIPI_DCS_GET_DISPLAY_ID,
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+ MIPI_DCS_GET_RED_CHANNEL,
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+ MIPI_DCS_GET_GREEN_CHANNEL,
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+ MIPI_DCS_GET_BLUE_CHANNEL,
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+ MIPI_DCS_GET_DISPLAY_STATUS,
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+ MIPI_DCS_GET_POWER_MODE,
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+ MIPI_DCS_GET_ADDRESS_MODE,
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+ MIPI_DCS_GET_PIXEL_FORMAT,
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+ MIPI_DCS_GET_DISPLAY_MODE,
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+ MIPI_DCS_GET_SIGNAL_MODE,
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+ MIPI_DCS_GET_DIAGNOSTIC_RESULT,
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+ MIPI_DCS_READ_MEMORY_START,
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+ MIPI_DCS_READ_MEMORY_CONTINUE,
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+ MIPI_DCS_GET_SCANLINE,
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+ MIPI_DCS_GET_DISPLAY_BRIGHTNESS,
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+ MIPI_DCS_GET_CONTROL_DISPLAY,
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+ MIPI_DCS_GET_POWER_SAVE,
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+ MIPI_DCS_GET_CABC_MIN_BRIGHTNESS,
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+ MIPI_DCS_READ_DDB_START,
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+ MIPI_DCS_READ_DDB_CONTINUE,
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+ 0, /* sentinel */
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+};
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+
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+static bool mipi_dbi_command_is_read(struct mipi_dbi *mipi, u8 cmd)
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+{
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+ unsigned int i;
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+
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+ if (!mipi->read_commands)
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+ return false;
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+
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+ for (i = 0; i < 0xff; i++) {
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+ if (!mipi->read_commands[i])
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+ return false;
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+ if (cmd == mipi->read_commands[i])
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+ return true;
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+ }
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+
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+ return false;
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+}
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+
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+/**
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+ * mipi_dbi_command_read - MIPI DCS read command
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+ * @mipi: MIPI structure
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+ * @cmd: Command
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+ * @val: Value read
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+ *
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+ * Send MIPI DCS read command to the controller.
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+ *
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+ * Returns:
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+ * Zero on success, negative error code on failure.
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+ */
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+int mipi_dbi_command_read(struct mipi_dbi *mipi, u8 cmd, u8 *val)
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+{
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+ if (!mipi->read_commands)
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+ return -EACCES;
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+
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+ if (!mipi_dbi_command_is_read(mipi, cmd))
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+ return -EINVAL;
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+
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+ return mipi_dbi_command_buf(mipi, cmd, val, 1);
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+}
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+EXPORT_SYMBOL(mipi_dbi_command_read);
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+
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+/**
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+ * mipi_dbi_command_buf - MIPI DCS command with parameter(s) in an array
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+ * @mipi: MIPI structure
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+ * @cmd: Command
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+ * @data: Parameter buffer
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+ * @len: Buffer length
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+ *
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+ * Returns:
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+ * Zero on success, negative error code on failure.
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+ */
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+int mipi_dbi_command_buf(struct mipi_dbi *mipi, u8 cmd, u8 *data, size_t len)
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+{
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+ int ret;
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+
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+ mutex_lock(&mipi->cmdlock);
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+ ret = mipi->command(mipi, cmd, data, len);
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+ mutex_unlock(&mipi->cmdlock);
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+
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+ return ret;
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+}
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+EXPORT_SYMBOL(mipi_dbi_command_buf);
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+
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+static int mipi_dbi_buf_copy(void *dst, struct drm_framebuffer *fb,
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+ struct drm_clip_rect *clip, bool swap)
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+{
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+ struct drm_gem_cma_object *cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
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+ struct dma_buf_attachment *import_attach = cma_obj->base.import_attach;
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+ struct drm_format_name_buf format_name;
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+ void *src = cma_obj->vaddr;
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+ int ret = 0;
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+
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+ if (import_attach) {
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+ ret = dma_buf_begin_cpu_access(import_attach->dmabuf,
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+ DMA_FROM_DEVICE);
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+ if (ret)
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+ return ret;
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+ }
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+
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+ switch (fb->format->format) {
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+ case DRM_FORMAT_RGB565:
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+ if (swap)
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+ tinydrm_swab16(dst, src, fb, clip);
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+ else
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+ tinydrm_memcpy(dst, src, fb, clip);
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+ break;
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+ case DRM_FORMAT_XRGB8888:
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+ tinydrm_xrgb8888_to_rgb565(dst, src, fb, clip, swap);
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+ break;
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+ default:
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+ dev_err_once(fb->dev->dev, "Format is not supported: %s\n",
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+ drm_get_format_name(fb->format->format,
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+ &format_name));
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+ return -EINVAL;
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+ }
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+
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+ if (import_attach)
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+ ret = dma_buf_end_cpu_access(import_attach->dmabuf,
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+ DMA_FROM_DEVICE);
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+ return ret;
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+}
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+
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+static int mipi_dbi_fb_dirty(struct drm_framebuffer *fb,
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+ struct drm_file *file_priv,
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+ unsigned int flags, unsigned int color,
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+ struct drm_clip_rect *clips,
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+ unsigned int num_clips)
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+{
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+ struct drm_gem_cma_object *cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
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+ struct tinydrm_device *tdev = fb->dev->dev_private;
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+ struct mipi_dbi *mipi = mipi_dbi_from_tinydrm(tdev);
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+ bool swap = mipi->swap_bytes;
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+ struct drm_clip_rect clip;
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+ int ret = 0;
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+ bool full;
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+ void *tr;
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+
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+ mutex_lock(&tdev->dirty_lock);
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+
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+ if (!mipi->enabled)
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+ goto out_unlock;
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+
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+ /* fbdev can flush even when we're not interested */
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+ if (tdev->pipe.plane.fb != fb)
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+ goto out_unlock;
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+
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+ full = tinydrm_merge_clips(&clip, clips, num_clips, flags,
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+ fb->width, fb->height);
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+
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+ DRM_DEBUG("Flushing [FB:%d] x1=%u, x2=%u, y1=%u, y2=%u\n", fb->base.id,
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+ clip.x1, clip.x2, clip.y1, clip.y2);
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+
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+ if (!mipi->dc || !full || swap ||
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+ fb->format->format == DRM_FORMAT_XRGB8888) {
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+ tr = mipi->tx_buf;
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+ ret = mipi_dbi_buf_copy(mipi->tx_buf, fb, &clip, swap);
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+ if (ret)
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+ goto out_unlock;
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+ } else {
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+ tr = cma_obj->vaddr;
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+ }
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+
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+ mipi_dbi_command(mipi, MIPI_DCS_SET_COLUMN_ADDRESS,
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+ (clip.x1 >> 8) & 0xFF, clip.x1 & 0xFF,
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+ (clip.x2 >> 8) & 0xFF, (clip.x2 - 1) & 0xFF);
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+ mipi_dbi_command(mipi, MIPI_DCS_SET_PAGE_ADDRESS,
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+ (clip.y1 >> 8) & 0xFF, clip.y1 & 0xFF,
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+ (clip.y2 >> 8) & 0xFF, (clip.y2 - 1) & 0xFF);
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+
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+ ret = mipi_dbi_command_buf(mipi, MIPI_DCS_WRITE_MEMORY_START, tr,
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+ (clip.x2 - clip.x1) * (clip.y2 - clip.y1) * 2);
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+
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+out_unlock:
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+ mutex_unlock(&tdev->dirty_lock);
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+
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+ if (ret)
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+ dev_err_once(fb->dev->dev, "Failed to update display %d\n",
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+ ret);
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+
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+ return ret;
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+}
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+
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+static const struct drm_framebuffer_funcs mipi_dbi_fb_funcs = {
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+ .destroy = drm_fb_cma_destroy,
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+ .create_handle = drm_fb_cma_create_handle,
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+ .dirty = mipi_dbi_fb_dirty,
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+};
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+
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+/**
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+ * mipi_dbi_pipe_enable - MIPI DBI pipe enable helper
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+ * @pipe: Display pipe
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+ * @crtc_state: CRTC state
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+ *
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+ * This function enables backlight. Drivers can use this as their
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+ * &drm_simple_display_pipe_funcs->enable callback.
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+ */
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+void mipi_dbi_pipe_enable(struct drm_simple_display_pipe *pipe,
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+ struct drm_crtc_state *crtc_state)
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+{
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+ struct tinydrm_device *tdev = pipe_to_tinydrm(pipe);
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+ struct mipi_dbi *mipi = mipi_dbi_from_tinydrm(tdev);
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+ struct drm_framebuffer *fb = pipe->plane.fb;
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+
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+ DRM_DEBUG_KMS("\n");
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+
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+ mipi->enabled = true;
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+ if (fb)
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+ fb->funcs->dirty(fb, NULL, 0, 0, NULL, 0);
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+
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+ tinydrm_enable_backlight(mipi->backlight);
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+}
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+EXPORT_SYMBOL(mipi_dbi_pipe_enable);
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+
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+static void mipi_dbi_blank(struct mipi_dbi *mipi)
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+{
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+ struct drm_device *drm = mipi->tinydrm.drm;
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+ u16 height = drm->mode_config.min_height;
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+ u16 width = drm->mode_config.min_width;
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+ size_t len = width * height * 2;
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+
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+ memset(mipi->tx_buf, 0, len);
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+
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+ mipi_dbi_command(mipi, MIPI_DCS_SET_COLUMN_ADDRESS, 0, 0,
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+ (width >> 8) & 0xFF, (width - 1) & 0xFF);
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+ mipi_dbi_command(mipi, MIPI_DCS_SET_PAGE_ADDRESS, 0, 0,
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+ (height >> 8) & 0xFF, (height - 1) & 0xFF);
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+ mipi_dbi_command_buf(mipi, MIPI_DCS_WRITE_MEMORY_START,
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+ (u8 *)mipi->tx_buf, len);
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+}
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+
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+/**
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+ * mipi_dbi_pipe_disable - MIPI DBI pipe disable helper
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+ * @pipe: Display pipe
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+ *
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+ * This function disables backlight if present or if not the
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+ * display memory is blanked. Drivers can use this as their
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+ * &drm_simple_display_pipe_funcs->disable callback.
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+ */
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+void mipi_dbi_pipe_disable(struct drm_simple_display_pipe *pipe)
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+{
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+ struct tinydrm_device *tdev = pipe_to_tinydrm(pipe);
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+ struct mipi_dbi *mipi = mipi_dbi_from_tinydrm(tdev);
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+
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+ DRM_DEBUG_KMS("\n");
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+
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+ mipi->enabled = false;
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+
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+ if (mipi->backlight)
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+ tinydrm_disable_backlight(mipi->backlight);
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+ else
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+ mipi_dbi_blank(mipi);
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+}
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+EXPORT_SYMBOL(mipi_dbi_pipe_disable);
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+
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+static const uint32_t mipi_dbi_formats[] = {
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+ DRM_FORMAT_RGB565,
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+ DRM_FORMAT_XRGB8888,
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+};
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+
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+/**
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+ * mipi_dbi_init - MIPI DBI initialization
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+ * @dev: Parent device
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+ * @mipi: &mipi_dbi structure to initialize
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+ * @pipe_funcs: Display pipe functions
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+ * @driver: DRM driver
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+ * @mode: Display mode
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+ * @rotation: Initial rotation in degrees Counter Clock Wise
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+ *
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+ * This function initializes a &mipi_dbi structure and it's underlying
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+ * @tinydrm_device. It also sets up the display pipeline.
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+ *
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+ * Supported formats: Native RGB565 and emulated XRGB8888.
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+ *
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+ * Objects created by this function will be automatically freed on driver
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+ * detach (devres).
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+ *
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+ * Returns:
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+ * Zero on success, negative error code on failure.
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+ */
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+int mipi_dbi_init(struct device *dev, struct mipi_dbi *mipi,
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+ const struct drm_simple_display_pipe_funcs *pipe_funcs,
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+ struct drm_driver *driver,
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+ const struct drm_display_mode *mode, unsigned int rotation)
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+{
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+ size_t bufsize = mode->vdisplay * mode->hdisplay * sizeof(u16);
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+ struct tinydrm_device *tdev = &mipi->tinydrm;
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+ int ret;
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+
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+ if (!mipi->command)
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+ return -EINVAL;
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+
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+ mutex_init(&mipi->cmdlock);
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+
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+ mipi->tx_buf = devm_kmalloc(dev, bufsize, GFP_KERNEL);
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+ if (!mipi->tx_buf)
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+ return -ENOMEM;
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+
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+ ret = devm_tinydrm_init(dev, tdev, &mipi_dbi_fb_funcs, driver);
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+ if (ret)
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+ return ret;
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+
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+ /* TODO: Maybe add DRM_MODE_CONNECTOR_SPI */
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+ ret = tinydrm_display_pipe_init(tdev, pipe_funcs,
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+ DRM_MODE_CONNECTOR_VIRTUAL,
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+ mipi_dbi_formats,
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|
|
+ ARRAY_SIZE(mipi_dbi_formats), mode,
|
|
|
+ rotation);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+
|
|
|
+ tdev->drm->mode_config.preferred_depth = 16;
|
|
|
+ mipi->rotation = rotation;
|
|
|
+
|
|
|
+ drm_mode_config_reset(tdev->drm);
|
|
|
+
|
|
|
+ DRM_DEBUG_KMS("preferred_depth=%u, rotation = %u\n",
|
|
|
+ tdev->drm->mode_config.preferred_depth, rotation);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+EXPORT_SYMBOL(mipi_dbi_init);
|
|
|
+
|
|
|
+/**
|
|
|
+ * mipi_dbi_hw_reset - Hardware reset of controller
|
|
|
+ * @mipi: MIPI DBI structure
|
|
|
+ *
|
|
|
+ * Reset controller if the &mipi_dbi->reset gpio is set.
|
|
|
+ */
|
|
|
+void mipi_dbi_hw_reset(struct mipi_dbi *mipi)
|
|
|
+{
|
|
|
+ if (!mipi->reset)
|
|
|
+ return;
|
|
|
+
|
|
|
+ gpiod_set_value_cansleep(mipi->reset, 0);
|
|
|
+ msleep(20);
|
|
|
+ gpiod_set_value_cansleep(mipi->reset, 1);
|
|
|
+ msleep(120);
|
|
|
+}
|
|
|
+EXPORT_SYMBOL(mipi_dbi_hw_reset);
|
|
|
+
|
|
|
+/**
|
|
|
+ * mipi_dbi_display_is_on - Check if display is on
|
|
|
+ * @mipi: MIPI DBI structure
|
|
|
+ *
|
|
|
+ * This function checks the Power Mode register (if readable) to see if
|
|
|
+ * display output is turned on. This can be used to see if the bootloader
|
|
|
+ * has already turned on the display avoiding flicker when the pipeline is
|
|
|
+ * enabled.
|
|
|
+ *
|
|
|
+ * Returns:
|
|
|
+ * true if the display can be verified to be on, false otherwise.
|
|
|
+ */
|
|
|
+bool mipi_dbi_display_is_on(struct mipi_dbi *mipi)
|
|
|
+{
|
|
|
+ u8 val;
|
|
|
+
|
|
|
+ if (mipi_dbi_command_read(mipi, MIPI_DCS_GET_POWER_MODE, &val))
|
|
|
+ return false;
|
|
|
+
|
|
|
+ val &= ~DCS_POWER_MODE_RESERVED_MASK;
|
|
|
+
|
|
|
+ if (val != (DCS_POWER_MODE_DISPLAY |
|
|
|
+ DCS_POWER_MODE_DISPLAY_NORMAL_MODE | DCS_POWER_MODE_SLEEP_MODE))
|
|
|
+ return false;
|
|
|
+
|
|
|
+ DRM_DEBUG_DRIVER("Display is ON\n");
|
|
|
+
|
|
|
+ return true;
|
|
|
+}
|
|
|
+EXPORT_SYMBOL(mipi_dbi_display_is_on);
|
|
|
+
|
|
|
+#if IS_ENABLED(CONFIG_SPI)
|
|
|
+
|
|
|
+/*
|
|
|
+ * Many controllers have a max speed of 10MHz, but can be pushed way beyond
|
|
|
+ * that. Increase reliability by running pixel data at max speed and the rest
|
|
|
+ * at 10MHz, preventing transfer glitches from messing up the init settings.
|
|
|
+ */
|
|
|
+static u32 mipi_dbi_spi_cmd_max_speed(struct spi_device *spi, size_t len)
|
|
|
+{
|
|
|
+ if (len > 64)
|
|
|
+ return 0; /* use default */
|
|
|
+
|
|
|
+ return min_t(u32, 10000000, spi->max_speed_hz);
|
|
|
+}
|
|
|
+
|
|
|
+/*
|
|
|
+ * MIPI DBI Type C Option 1
|
|
|
+ *
|
|
|
+ * If the SPI controller doesn't have 9 bits per word support,
|
|
|
+ * use blocks of 9 bytes to send 8x 9-bit words using a 8-bit SPI transfer.
|
|
|
+ * Pad partial blocks with MIPI_DCS_NOP (zero).
|
|
|
+ * This is how the D/C bit (x) is added:
|
|
|
+ * x7654321
|
|
|
+ * 0x765432
|
|
|
+ * 10x76543
|
|
|
+ * 210x7654
|
|
|
+ * 3210x765
|
|
|
+ * 43210x76
|
|
|
+ * 543210x7
|
|
|
+ * 6543210x
|
|
|
+ * 76543210
|
|
|
+ */
|
|
|
+
|
|
|
+static int mipi_dbi_spi1e_transfer(struct mipi_dbi *mipi, int dc,
|
|
|
+ const void *buf, size_t len,
|
|
|
+ unsigned int bpw)
|
|
|
+{
|
|
|
+ bool swap_bytes = (bpw == 16 && tinydrm_machine_little_endian());
|
|
|
+ size_t chunk, max_chunk = mipi->tx_buf9_len;
|
|
|
+ struct spi_device *spi = mipi->spi;
|
|
|
+ struct spi_transfer tr = {
|
|
|
+ .tx_buf = mipi->tx_buf9,
|
|
|
+ .bits_per_word = 8,
|
|
|
+ };
|
|
|
+ struct spi_message m;
|
|
|
+ const u8 *src = buf;
|
|
|
+ int i, ret;
|
|
|
+ u8 *dst;
|
|
|
+
|
|
|
+ if (drm_debug & DRM_UT_DRIVER)
|
|
|
+ pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n",
|
|
|
+ __func__, dc, max_chunk);
|
|
|
+
|
|
|
+ tr.speed_hz = mipi_dbi_spi_cmd_max_speed(spi, len);
|
|
|
+ spi_message_init_with_transfers(&m, &tr, 1);
|
|
|
+
|
|
|
+ if (!dc) {
|
|
|
+ if (WARN_ON_ONCE(len != 1))
|
|
|
+ return -EINVAL;
|
|
|
+
|
|
|
+ /* Command: pad no-op's (zeroes) at beginning of block */
|
|
|
+ dst = mipi->tx_buf9;
|
|
|
+ memset(dst, 0, 9);
|
|
|
+ dst[8] = *src;
|
|
|
+ tr.len = 9;
|
|
|
+
|
|
|
+ tinydrm_dbg_spi_message(spi, &m);
|
|
|
+
|
|
|
+ return spi_sync(spi, &m);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* max with room for adding one bit per byte */
|
|
|
+ max_chunk = max_chunk / 9 * 8;
|
|
|
+ /* but no bigger than len */
|
|
|
+ max_chunk = min(max_chunk, len);
|
|
|
+ /* 8 byte blocks */
|
|
|
+ max_chunk = max_t(size_t, 8, max_chunk & ~0x7);
|
|
|
+
|
|
|
+ while (len) {
|
|
|
+ size_t added = 0;
|
|
|
+
|
|
|
+ chunk = min(len, max_chunk);
|
|
|
+ len -= chunk;
|
|
|
+ dst = mipi->tx_buf9;
|
|
|
+
|
|
|
+ if (chunk < 8) {
|
|
|
+ u8 val, carry = 0;
|
|
|
+
|
|
|
+ /* Data: pad no-op's (zeroes) at end of block */
|
|
|
+ memset(dst, 0, 9);
|
|
|
+
|
|
|
+ if (swap_bytes) {
|
|
|
+ for (i = 1; i < (chunk + 1); i++) {
|
|
|
+ val = src[1];
|
|
|
+ *dst++ = carry | BIT(8 - i) | (val >> i);
|
|
|
+ carry = val << (8 - i);
|
|
|
+ i++;
|
|
|
+ val = src[0];
|
|
|
+ *dst++ = carry | BIT(8 - i) | (val >> i);
|
|
|
+ carry = val << (8 - i);
|
|
|
+ src += 2;
|
|
|
+ }
|
|
|
+ *dst++ = carry;
|
|
|
+ } else {
|
|
|
+ for (i = 1; i < (chunk + 1); i++) {
|
|
|
+ val = *src++;
|
|
|
+ *dst++ = carry | BIT(8 - i) | (val >> i);
|
|
|
+ carry = val << (8 - i);
|
|
|
+ }
|
|
|
+ *dst++ = carry;
|
|
|
+ }
|
|
|
+
|
|
|
+ chunk = 8;
|
|
|
+ added = 1;
|
|
|
+ } else {
|
|
|
+ for (i = 0; i < chunk; i += 8) {
|
|
|
+ if (swap_bytes) {
|
|
|
+ *dst++ = BIT(7) | (src[1] >> 1);
|
|
|
+ *dst++ = (src[1] << 7) | BIT(6) | (src[0] >> 2);
|
|
|
+ *dst++ = (src[0] << 6) | BIT(5) | (src[3] >> 3);
|
|
|
+ *dst++ = (src[3] << 5) | BIT(4) | (src[2] >> 4);
|
|
|
+ *dst++ = (src[2] << 4) | BIT(3) | (src[5] >> 5);
|
|
|
+ *dst++ = (src[5] << 3) | BIT(2) | (src[4] >> 6);
|
|
|
+ *dst++ = (src[4] << 2) | BIT(1) | (src[7] >> 7);
|
|
|
+ *dst++ = (src[7] << 1) | BIT(0);
|
|
|
+ *dst++ = src[6];
|
|
|
+ } else {
|
|
|
+ *dst++ = BIT(7) | (src[0] >> 1);
|
|
|
+ *dst++ = (src[0] << 7) | BIT(6) | (src[1] >> 2);
|
|
|
+ *dst++ = (src[1] << 6) | BIT(5) | (src[2] >> 3);
|
|
|
+ *dst++ = (src[2] << 5) | BIT(4) | (src[3] >> 4);
|
|
|
+ *dst++ = (src[3] << 4) | BIT(3) | (src[4] >> 5);
|
|
|
+ *dst++ = (src[4] << 3) | BIT(2) | (src[5] >> 6);
|
|
|
+ *dst++ = (src[5] << 2) | BIT(1) | (src[6] >> 7);
|
|
|
+ *dst++ = (src[6] << 1) | BIT(0);
|
|
|
+ *dst++ = src[7];
|
|
|
+ }
|
|
|
+
|
|
|
+ src += 8;
|
|
|
+ added++;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ tr.len = chunk + added;
|
|
|
+
|
|
|
+ tinydrm_dbg_spi_message(spi, &m);
|
|
|
+ ret = spi_sync(spi, &m);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+ };
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static int mipi_dbi_spi1_transfer(struct mipi_dbi *mipi, int dc,
|
|
|
+ const void *buf, size_t len,
|
|
|
+ unsigned int bpw)
|
|
|
+{
|
|
|
+ struct spi_device *spi = mipi->spi;
|
|
|
+ struct spi_transfer tr = {
|
|
|
+ .bits_per_word = 9,
|
|
|
+ };
|
|
|
+ const u16 *src16 = buf;
|
|
|
+ const u8 *src8 = buf;
|
|
|
+ struct spi_message m;
|
|
|
+ size_t max_chunk;
|
|
|
+ u16 *dst16;
|
|
|
+ int ret;
|
|
|
+
|
|
|
+ if (!tinydrm_spi_bpw_supported(spi, 9))
|
|
|
+ return mipi_dbi_spi1e_transfer(mipi, dc, buf, len, bpw);
|
|
|
+
|
|
|
+ tr.speed_hz = mipi_dbi_spi_cmd_max_speed(spi, len);
|
|
|
+ max_chunk = mipi->tx_buf9_len;
|
|
|
+ dst16 = mipi->tx_buf9;
|
|
|
+
|
|
|
+ if (drm_debug & DRM_UT_DRIVER)
|
|
|
+ pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n",
|
|
|
+ __func__, dc, max_chunk);
|
|
|
+
|
|
|
+ max_chunk = min(max_chunk / 2, len);
|
|
|
+
|
|
|
+ spi_message_init_with_transfers(&m, &tr, 1);
|
|
|
+ tr.tx_buf = dst16;
|
|
|
+
|
|
|
+ while (len) {
|
|
|
+ size_t chunk = min(len, max_chunk);
|
|
|
+ unsigned int i;
|
|
|
+
|
|
|
+ if (bpw == 16 && tinydrm_machine_little_endian()) {
|
|
|
+ for (i = 0; i < (chunk * 2); i += 2) {
|
|
|
+ dst16[i] = *src16 >> 8;
|
|
|
+ dst16[i + 1] = *src16++ & 0xFF;
|
|
|
+ if (dc) {
|
|
|
+ dst16[i] |= 0x0100;
|
|
|
+ dst16[i + 1] |= 0x0100;
|
|
|
+ }
|
|
|
+ }
|
|
|
+ } else {
|
|
|
+ for (i = 0; i < chunk; i++) {
|
|
|
+ dst16[i] = *src8++;
|
|
|
+ if (dc)
|
|
|
+ dst16[i] |= 0x0100;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ tr.len = chunk;
|
|
|
+ len -= chunk;
|
|
|
+
|
|
|
+ tinydrm_dbg_spi_message(spi, &m);
|
|
|
+ ret = spi_sync(spi, &m);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+ };
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static int mipi_dbi_typec1_command(struct mipi_dbi *mipi, u8 cmd,
|
|
|
+ u8 *parameters, size_t num)
|
|
|
+{
|
|
|
+ unsigned int bpw = (cmd == MIPI_DCS_WRITE_MEMORY_START) ? 16 : 8;
|
|
|
+ int ret;
|
|
|
+
|
|
|
+ if (mipi_dbi_command_is_read(mipi, cmd))
|
|
|
+ return -ENOTSUPP;
|
|
|
+
|
|
|
+ MIPI_DBI_DEBUG_COMMAND(cmd, parameters, num);
|
|
|
+
|
|
|
+ ret = mipi_dbi_spi1_transfer(mipi, 0, &cmd, 1, 8);
|
|
|
+ if (ret || !num)
|
|
|
+ return ret;
|
|
|
+
|
|
|
+ return mipi_dbi_spi1_transfer(mipi, 1, parameters, num, bpw);
|
|
|
+}
|
|
|
+
|
|
|
+/* MIPI DBI Type C Option 3 */
|
|
|
+
|
|
|
+static int mipi_dbi_typec3_command_read(struct mipi_dbi *mipi, u8 cmd,
|
|
|
+ u8 *data, size_t len)
|
|
|
+{
|
|
|
+ struct spi_device *spi = mipi->spi;
|
|
|
+ u32 speed_hz = min_t(u32, MIPI_DBI_MAX_SPI_READ_SPEED,
|
|
|
+ spi->max_speed_hz / 2);
|
|
|
+ struct spi_transfer tr[2] = {
|
|
|
+ {
|
|
|
+ .speed_hz = speed_hz,
|
|
|
+ .tx_buf = &cmd,
|
|
|
+ .len = 1,
|
|
|
+ }, {
|
|
|
+ .speed_hz = speed_hz,
|
|
|
+ .len = len,
|
|
|
+ },
|
|
|
+ };
|
|
|
+ struct spi_message m;
|
|
|
+ u8 *buf;
|
|
|
+ int ret;
|
|
|
+
|
|
|
+ if (!len)
|
|
|
+ return -EINVAL;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Support non-standard 24-bit and 32-bit Nokia read commands which
|
|
|
+ * start with a dummy clock, so we need to read an extra byte.
|
|
|
+ */
|
|
|
+ if (cmd == MIPI_DCS_GET_DISPLAY_ID ||
|
|
|
+ cmd == MIPI_DCS_GET_DISPLAY_STATUS) {
|
|
|
+ if (!(len == 3 || len == 4))
|
|
|
+ return -EINVAL;
|
|
|
+
|
|
|
+ tr[1].len = len + 1;
|
|
|
+ }
|
|
|
+
|
|
|
+ buf = kmalloc(tr[1].len, GFP_KERNEL);
|
|
|
+ if (!buf)
|
|
|
+ return -ENOMEM;
|
|
|
+
|
|
|
+ tr[1].rx_buf = buf;
|
|
|
+ gpiod_set_value_cansleep(mipi->dc, 0);
|
|
|
+
|
|
|
+ spi_message_init_with_transfers(&m, tr, ARRAY_SIZE(tr));
|
|
|
+ ret = spi_sync(spi, &m);
|
|
|
+ if (ret)
|
|
|
+ goto err_free;
|
|
|
+
|
|
|
+ tinydrm_dbg_spi_message(spi, &m);
|
|
|
+
|
|
|
+ if (tr[1].len == len) {
|
|
|
+ memcpy(data, buf, len);
|
|
|
+ } else {
|
|
|
+ unsigned int i;
|
|
|
+
|
|
|
+ for (i = 0; i < len; i++)
|
|
|
+ data[i] = (buf[i] << 1) | !!(buf[i + 1] & BIT(7));
|
|
|
+ }
|
|
|
+
|
|
|
+ MIPI_DBI_DEBUG_COMMAND(cmd, data, len);
|
|
|
+
|
|
|
+err_free:
|
|
|
+ kfree(buf);
|
|
|
+
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
+static int mipi_dbi_typec3_command(struct mipi_dbi *mipi, u8 cmd,
|
|
|
+ u8 *par, size_t num)
|
|
|
+{
|
|
|
+ struct spi_device *spi = mipi->spi;
|
|
|
+ unsigned int bpw = 8;
|
|
|
+ u32 speed_hz;
|
|
|
+ int ret;
|
|
|
+
|
|
|
+ if (mipi_dbi_command_is_read(mipi, cmd))
|
|
|
+ return mipi_dbi_typec3_command_read(mipi, cmd, par, num);
|
|
|
+
|
|
|
+ MIPI_DBI_DEBUG_COMMAND(cmd, par, num);
|
|
|
+
|
|
|
+ gpiod_set_value_cansleep(mipi->dc, 0);
|
|
|
+ speed_hz = mipi_dbi_spi_cmd_max_speed(spi, 1);
|
|
|
+ ret = tinydrm_spi_transfer(spi, speed_hz, NULL, 8, &cmd, 1);
|
|
|
+ if (ret || !num)
|
|
|
+ return ret;
|
|
|
+
|
|
|
+ if (cmd == MIPI_DCS_WRITE_MEMORY_START && !mipi->swap_bytes)
|
|
|
+ bpw = 16;
|
|
|
+
|
|
|
+ gpiod_set_value_cansleep(mipi->dc, 1);
|
|
|
+ speed_hz = mipi_dbi_spi_cmd_max_speed(spi, num);
|
|
|
+
|
|
|
+ return tinydrm_spi_transfer(spi, speed_hz, NULL, bpw, par, num);
|
|
|
+}
|
|
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+
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+/**
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+ * mipi_dbi_spi_init - Initialize MIPI DBI SPI interfaced controller
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+ * @spi: SPI device
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+ * @dc: D/C gpio (optional)
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+ * @mipi: &mipi_dbi structure to initialize
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+ * @pipe_funcs: Display pipe functions
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+ * @driver: DRM driver
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+ * @mode: Display mode
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+ * @rotation: Initial rotation in degrees Counter Clock Wise
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+ *
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+ * This function sets &mipi_dbi->command, enables &mipi->read_commands for the
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+ * usual read commands and initializes @mipi using mipi_dbi_init().
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+ *
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+ * If @dc is set, a Type C Option 3 interface is assumed, if not
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+ * Type C Option 1.
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+ *
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+ * If the SPI master driver doesn't support the necessary bits per word,
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+ * the following transformation is used:
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+ *
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+ * - 9-bit: reorder buffer as 9x 8-bit words, padded with no-op command.
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+ * - 16-bit: if big endian send as 8-bit, if little endian swap bytes
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+ *
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+ * Returns:
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+ * Zero on success, negative error code on failure.
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+ */
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+int mipi_dbi_spi_init(struct spi_device *spi, struct mipi_dbi *mipi,
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+ struct gpio_desc *dc,
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+ const struct drm_simple_display_pipe_funcs *pipe_funcs,
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+ struct drm_driver *driver,
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+ const struct drm_display_mode *mode,
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+ unsigned int rotation)
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+{
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+ size_t tx_size = tinydrm_spi_max_transfer_size(spi, 0);
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+ struct device *dev = &spi->dev;
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+ int ret;
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+
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+ if (tx_size < 16) {
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+ DRM_ERROR("SPI transmit buffer too small: %zu\n", tx_size);
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+ return -EINVAL;
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+ }
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+
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+ /*
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+ * Even though it's not the SPI device that does DMA (the master does),
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+ * the dma mask is necessary for the dma_alloc_wc() in
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+ * drm_gem_cma_create(). The dma_addr returned will be a physical
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+ * adddress which might be different from the bus address, but this is
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+ * not a problem since the address will not be used.
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+ * The virtual address is used in the transfer and the SPI core
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+ * re-maps it on the SPI master device using the DMA streaming API
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+ * (spi_map_buf()).
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+ */
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+ if (!dev->coherent_dma_mask) {
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+ ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32));
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+ if (ret) {
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+ dev_warn(dev, "Failed to set dma mask %d\n", ret);
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+ return ret;
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+ }
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+ }
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+
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+ mipi->spi = spi;
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+ mipi->read_commands = mipi_dbi_dcs_read_commands;
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+
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+ if (dc) {
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+ mipi->command = mipi_dbi_typec3_command;
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+ mipi->dc = dc;
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+ if (tinydrm_machine_little_endian() &&
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+ !tinydrm_spi_bpw_supported(spi, 16))
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+ mipi->swap_bytes = true;
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+ } else {
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+ mipi->command = mipi_dbi_typec1_command;
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+ mipi->tx_buf9_len = tx_size;
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+ mipi->tx_buf9 = devm_kmalloc(dev, tx_size, GFP_KERNEL);
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+ if (!mipi->tx_buf9)
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+ return -ENOMEM;
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+ }
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+
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+ return mipi_dbi_init(dev, mipi, pipe_funcs, driver, mode, rotation);
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+}
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+EXPORT_SYMBOL(mipi_dbi_spi_init);
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+
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+#endif /* CONFIG_SPI */
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+
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+#ifdef CONFIG_DEBUG_FS
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+
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+static ssize_t mipi_dbi_debugfs_command_write(struct file *file,
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+ const char __user *ubuf,
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+ size_t count, loff_t *ppos)
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+{
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+ struct seq_file *m = file->private_data;
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+ struct mipi_dbi *mipi = m->private;
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+ u8 val, cmd, parameters[64];
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+ char *buf, *pos, *token;
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+ unsigned int i;
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+ int ret;
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+
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+ buf = memdup_user_nul(ubuf, count);
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+ if (IS_ERR(buf))
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+ return PTR_ERR(buf);
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+
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+ /* strip trailing whitespace */
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+ for (i = count - 1; i > 0; i--)
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+ if (isspace(buf[i]))
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+ buf[i] = '\0';
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+ else
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+ break;
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+ i = 0;
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+ pos = buf;
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+ while (pos) {
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+ token = strsep(&pos, " ");
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+ if (!token) {
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+ ret = -EINVAL;
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+ goto err_free;
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+ }
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+
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+ ret = kstrtou8(token, 16, &val);
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+ if (ret < 0)
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+ goto err_free;
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+
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+ if (token == buf)
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+ cmd = val;
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+ else
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+ parameters[i++] = val;
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+
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+ if (i == 64) {
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+ ret = -E2BIG;
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+ goto err_free;
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+ }
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+ }
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+
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+ ret = mipi_dbi_command_buf(mipi, cmd, parameters, i);
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+
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+err_free:
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+ kfree(buf);
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+
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+ return ret < 0 ? ret : count;
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+}
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+
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+static int mipi_dbi_debugfs_command_show(struct seq_file *m, void *unused)
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+{
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+ struct mipi_dbi *mipi = m->private;
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+ u8 cmd, val[4];
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+ size_t len, i;
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+ int ret;
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+
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+ for (cmd = 0; cmd < 255; cmd++) {
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+ if (!mipi_dbi_command_is_read(mipi, cmd))
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+ continue;
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+
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+ switch (cmd) {
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+ case MIPI_DCS_READ_MEMORY_START:
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+ case MIPI_DCS_READ_MEMORY_CONTINUE:
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+ len = 2;
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+ break;
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+ case MIPI_DCS_GET_DISPLAY_ID:
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+ len = 3;
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+ break;
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+ case MIPI_DCS_GET_DISPLAY_STATUS:
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+ len = 4;
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|
+ break;
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+ default:
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+ len = 1;
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|
+ break;
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|
+ }
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|
+
|
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|
+ seq_printf(m, "%02x: ", cmd);
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|
+ ret = mipi_dbi_command_buf(mipi, cmd, val, len);
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+ if (ret) {
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|
+ seq_puts(m, "XX\n");
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|
+ continue;
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|
+ }
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|
+
|
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|
+ for (i = 0; i < len; i++)
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|
|
+ seq_printf(m, "%02x", val[i]);
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|
|
+ seq_puts(m, "\n");
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|
|
+ }
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|
+
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|
|
+ return 0;
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|
+}
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|
|
+
|
|
|
+static int mipi_dbi_debugfs_command_open(struct inode *inode,
|
|
|
+ struct file *file)
|
|
|
+{
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|
|
+ return single_open(file, mipi_dbi_debugfs_command_show,
|
|
|
+ inode->i_private);
|
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|
+}
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|
|
+
|
|
|
+static const struct file_operations mipi_dbi_debugfs_command_fops = {
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|
|
+ .owner = THIS_MODULE,
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|
|
+ .open = mipi_dbi_debugfs_command_open,
|
|
|
+ .read = seq_read,
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|
|
+ .llseek = seq_lseek,
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|
+ .release = single_release,
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|
+ .write = mipi_dbi_debugfs_command_write,
|
|
|
+};
|
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|
+
|
|
|
+static const struct drm_info_list mipi_dbi_debugfs_list[] = {
|
|
|
+ { "fb", drm_fb_cma_debugfs_show, 0 },
|
|
|
+};
|
|
|
+
|
|
|
+/**
|
|
|
+ * mipi_dbi_debugfs_init - Create debugfs entries
|
|
|
+ * @minor: DRM minor
|
|
|
+ *
|
|
|
+ * This function creates a 'command' debugfs file for sending commands to the
|
|
|
+ * controller or getting the read command values.
|
|
|
+ * Drivers can use this as their &drm_driver->debugfs_init callback.
|
|
|
+ *
|
|
|
+ * Returns:
|
|
|
+ * Zero on success, negative error code on failure.
|
|
|
+ */
|
|
|
+int mipi_dbi_debugfs_init(struct drm_minor *minor)
|
|
|
+{
|
|
|
+ struct tinydrm_device *tdev = minor->dev->dev_private;
|
|
|
+ struct mipi_dbi *mipi = mipi_dbi_from_tinydrm(tdev);
|
|
|
+ umode_t mode = S_IFREG | S_IWUSR;
|
|
|
+
|
|
|
+ if (mipi->read_commands)
|
|
|
+ mode |= S_IRUGO;
|
|
|
+ debugfs_create_file("command", mode, minor->debugfs_root, mipi,
|
|
|
+ &mipi_dbi_debugfs_command_fops);
|
|
|
+
|
|
|
+ return drm_debugfs_create_files(mipi_dbi_debugfs_list,
|
|
|
+ ARRAY_SIZE(mipi_dbi_debugfs_list),
|
|
|
+ minor->debugfs_root, minor);
|
|
|
+}
|
|
|
+EXPORT_SYMBOL(mipi_dbi_debugfs_init);
|
|
|
+
|
|
|
+#endif
|
|
|
+
|
|
|
+MODULE_LICENSE("GPL");
|
Dave Airlie