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@@ -505,6 +505,20 @@ static void vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring *ring)
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amdgpu_ring_write(ring, VCN_CMD_PACKET_START << 1);
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amdgpu_ring_write(ring, VCN_CMD_PACKET_START << 1);
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}
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}
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+/**
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+ * vcn_v1_0_dec_ring_insert_end - insert a end command
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+ *
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+ * @ring: amdgpu_ring pointer
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+ *
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+ * Write a end command to the ring.
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+ */
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+static void vcn_v1_0_dec_ring_insert_end(struct amdgpu_ring *ring)
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+{
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+ amdgpu_ring_write(ring,
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+ PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
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+ amdgpu_ring_write(ring, VCN_CMD_PACKET_END << 1);
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+}
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+
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/**
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/**
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* vcn_v1_0_dec_ring_emit_fence - emit an fence & trap command
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* vcn_v1_0_dec_ring_emit_fence - emit an fence & trap command
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*
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*
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@@ -701,7 +715,7 @@ static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = {
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2 + /* vcn_v1_0_dec_ring_emit_hdp_invalidate */
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2 + /* vcn_v1_0_dec_ring_emit_hdp_invalidate */
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34 * AMDGPU_MAX_VMHUBS + /* vcn_v1_0_dec_ring_emit_vm_flush */
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34 * AMDGPU_MAX_VMHUBS + /* vcn_v1_0_dec_ring_emit_vm_flush */
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14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */
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14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */
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- 4,
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+ 6,
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.emit_ib_size = 8, /* vcn_v1_0_dec_ring_emit_ib */
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.emit_ib_size = 8, /* vcn_v1_0_dec_ring_emit_ib */
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.emit_ib = vcn_v1_0_dec_ring_emit_ib,
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.emit_ib = vcn_v1_0_dec_ring_emit_ib,
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.emit_fence = vcn_v1_0_dec_ring_emit_fence,
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.emit_fence = vcn_v1_0_dec_ring_emit_fence,
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@@ -711,6 +725,7 @@ static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = {
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.test_ib = amdgpu_vcn_dec_ring_test_ib,
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.test_ib = amdgpu_vcn_dec_ring_test_ib,
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.insert_nop = amdgpu_ring_insert_nop,
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.insert_nop = amdgpu_ring_insert_nop,
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.insert_start = vcn_v1_0_dec_ring_insert_start,
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.insert_start = vcn_v1_0_dec_ring_insert_start,
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+ .insert_end = vcn_v1_0_dec_ring_insert_end,
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.pad_ib = amdgpu_ring_generic_pad_ib,
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.pad_ib = amdgpu_ring_generic_pad_ib,
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.begin_use = amdgpu_vcn_ring_begin_use,
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.begin_use = amdgpu_vcn_ring_begin_use,
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.end_use = amdgpu_vcn_ring_end_use,
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.end_use = amdgpu_vcn_ring_end_use,
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