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@@ -36,6 +36,8 @@ g84_hdmi_ctrl(NV50_DISP_MTHD_V1)
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union {
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struct nv50_disp_sor_hdmi_pwr_v0 v0;
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} *args = data;
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+ struct packed_hdmi_infoframe avi_infoframe;
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+ struct packed_hdmi_infoframe vendor_infoframe;
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u32 ctrl;
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int ret = -ENOSYS;
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@@ -61,8 +63,17 @@ g84_hdmi_ctrl(NV50_DISP_MTHD_V1)
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+ args->v0.vendor_infoframe_length) < size)
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return -E2BIG;
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+ pack_hdmi_infoframe(&avi_infoframe,
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+ data,
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+ args->v0.avi_infoframe_length);
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+
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+ pack_hdmi_infoframe(&vendor_infoframe,
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+ data + args->v0.avi_infoframe_length,
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+ args->v0.vendor_infoframe_length);
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+
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if (!(ctrl & 0x40000000)) {
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nvkm_mask(device, 0x6165a4 + hoff, 0x40000000, 0x00000000);
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+ nvkm_mask(device, 0x61653c + hoff, 0x00000001, 0x00000000);
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nvkm_mask(device, 0x616520 + hoff, 0x00000001, 0x00000000);
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nvkm_mask(device, 0x616500 + hoff, 0x00000001, 0x00000000);
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return 0;
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@@ -70,12 +81,14 @@ g84_hdmi_ctrl(NV50_DISP_MTHD_V1)
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/* AVI InfoFrame */
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nvkm_mask(device, 0x616520 + hoff, 0x00000001, 0x00000000);
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- nvkm_wr32(device, 0x616528 + hoff, 0x000d0282);
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- nvkm_wr32(device, 0x61652c + hoff, 0x0000006f);
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- nvkm_wr32(device, 0x616530 + hoff, 0x00000000);
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- nvkm_wr32(device, 0x616534 + hoff, 0x00000000);
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- nvkm_wr32(device, 0x616538 + hoff, 0x00000000);
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- nvkm_mask(device, 0x616520 + hoff, 0x00000001, 0x00000001);
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+ if (args->v0.avi_infoframe_length) {
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+ nvkm_wr32(device, 0x616528 + hoff, avi_infoframe.header);
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+ nvkm_wr32(device, 0x61652c + hoff, avi_infoframe.subpack0_low);
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+ nvkm_wr32(device, 0x616530 + hoff, avi_infoframe.subpack0_high);
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+ nvkm_wr32(device, 0x616534 + hoff, avi_infoframe.subpack1_low);
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+ nvkm_wr32(device, 0x616538 + hoff, avi_infoframe.subpack1_high);
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+ nvkm_mask(device, 0x616520 + hoff, 0x00000001, 0x00000001);
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+ }
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/* Audio InfoFrame */
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nvkm_mask(device, 0x616500 + hoff, 0x00000001, 0x00000000);
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@@ -84,6 +97,18 @@ g84_hdmi_ctrl(NV50_DISP_MTHD_V1)
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nvkm_wr32(device, 0x616510 + hoff, 0x00000000);
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nvkm_mask(device, 0x616500 + hoff, 0x00000001, 0x00000001);
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+ /* Vendor InfoFrame */
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+ nvkm_mask(device, 0x61653c + hoff, 0x00010001, 0x00010000);
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+ if (args->v0.vendor_infoframe_length) {
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+ nvkm_wr32(device, 0x616544 + hoff, vendor_infoframe.header);
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+ nvkm_wr32(device, 0x616548 + hoff, vendor_infoframe.subpack0_low);
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+ nvkm_wr32(device, 0x61654c + hoff, vendor_infoframe.subpack0_high);
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+ /* Is there a second (or up to fourth?) set of subpack registers here? */
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+ /* nvkm_wr32(device, 0x616550 + hoff, vendor_infoframe->subpack1_low); */
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+ /* nvkm_wr32(device, 0x616554 + hoff, vendor_infoframe->subpack1_high); */
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+ nvkm_mask(device, 0x61653c + hoff, 0x00010001, 0x00010001);
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+ }
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+
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nvkm_mask(device, 0x6165d0 + hoff, 0x00070001, 0x00010001); /* SPARE, HW_CTS */
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nvkm_mask(device, 0x616568 + hoff, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */
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nvkm_mask(device, 0x616578 + hoff, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */
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