m68knommu: make ColdFire Pin Assignment register definitions absolute addresses

Make all definitions of the ColdFire Pin Assignment registers absolute
addresses. Currently some are relative to the MBAR peripheral region.

The various ColdFire parts use different methods to address the internal
registers, some are absolute, some are relative to peripheral regions
which can be mapped at different address ranges (such as the MBAR and IPSBAR
registers). We don't want to deal with this in the code when we are
accessing these registers, so make all register definitions the absolute
address - factoring out whether it is an offset into a peripheral region.

This makes them all consistently defined, and reduces the occasional bugs
caused by inconsistent definition of the register addresses.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>

arch/m68k/include/asm/m5206sim.h

@@ -85,9 +85,9 @@
 #define	MCFSIM_DMCR		0xc6		/* Default control */
 
 #ifdef CONFIG_M5206e
-#define	MCFSIM_PAR		0xca		/* Pin Assignment reg (r/w) */
+#define	MCFSIM_PAR		(MCF_MBAR + 0xca)	/* Pin Assignment */
 #else
-#define	MCFSIM_PAR		0xcb		/* Pin Assignment reg (r/w) */
+#define	MCFSIM_PAR		(MCF_MBAR + 0xcb)	/* Pin Assignment */
 #endif
 
 #define	MCFTIMER_BASE1		(MCF_MBAR + 0x100)	/* Base of TIMER1 */

arch/m68k/include/asm/m5249sim.h

@@ -29,7 +29,7 @@
 #define	MCFSIM_SYPCR		(MCF_MBAR + 0x01)	/* System Protection */
 #define	MCFSIM_SWIVR		(MCF_MBAR + 0x02)	/* SW Watchdog intr */
 #define	MCFSIM_SWSR		(MCF_MBAR + 0x03)	/* SW Watchdog srv */
-#define	MCFSIM_PAR		0x04		/* Pin Assignment reg (r/w) */
+#define	MCFSIM_PAR		(MCF_MBAR + 0x04)	/* Pin Assignment */
 #define	MCFSIM_IRQPAR		0x06		/* Interrupt Assignment reg (r/w) */
 #define	MCFSIM_MPARK		0x0C		/* BUS Master Control Reg*/
 #define	MCFSIM_IPR		(MCF_MBAR + 0x40)	/* Interrupt Pending */

arch/m68k/include/asm/m5307sim.h

@@ -27,7 +27,7 @@
 #define	MCFSIM_SYPCR		(MCF_MBAR + 0x01)	/* System Protection */
 #define	MCFSIM_SWIVR		(MCF_MBAR + 0x02)	/* SW Watchdog intr */
 #define	MCFSIM_SWSR		(MCF_MBAR + 0x03)	/* SW Watchdog service*/
-#define	MCFSIM_PAR		0x04		/* Pin Assignment reg (r/w) */
+#define	MCFSIM_PAR		(MCF_MBAR + 0x04)	/* Pin Assignment */
 #define	MCFSIM_IRQPAR		0x06		/* Interrupt Assignment reg (r/w) */
 #define	MCFSIM_PLLCR		0x08		/* PLL Control Reg*/
 #define	MCFSIM_MPARK		0x0C		/* BUS Master Control Reg*/

arch/m68k/include/asm/m5407sim.h

@@ -27,7 +27,7 @@
 #define	MCFSIM_SYPCR		(MCF_MBAR + 0x01)	/* System Protection */
 #define	MCFSIM_SWIVR		(MCF_MBAR + 0x02)	/* SW Watchdog intr */
 #define	MCFSIM_SWSR		(MCF_MBAR + 0x03)	/* SW Watchdog service*/
-#define	MCFSIM_PAR		0x04		/* Pin Assignment reg (r/w) */
+#define	MCFSIM_PAR		(MCF_MBAR + 0x04)	/* Pin Assignment */
 #define	MCFSIM_IRQPAR		0x06		/* Interrupt Assignment reg (r/w) */
 #define	MCFSIM_PLLCR		0x08		/* PLL Control Reg*/
 #define	MCFSIM_MPARK		0x0C		/* BUS Master Control Reg*/