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@@ -101,6 +101,7 @@ void __init arm_dt_init_cpu_maps(void)
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if (of_property_read_u32(cpu, "reg", &hwid)) {
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if (of_property_read_u32(cpu, "reg", &hwid)) {
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pr_debug(" * %s missing reg property\n",
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pr_debug(" * %s missing reg property\n",
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cpu->full_name);
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cpu->full_name);
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+ of_node_put(cpu);
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return;
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return;
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}
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}
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@@ -108,8 +109,10 @@ void __init arm_dt_init_cpu_maps(void)
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* 8 MSBs must be set to 0 in the DT since the reg property
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* 8 MSBs must be set to 0 in the DT since the reg property
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* defines the MPIDR[23:0].
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* defines the MPIDR[23:0].
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*/
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*/
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- if (hwid & ~MPIDR_HWID_BITMASK)
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+ if (hwid & ~MPIDR_HWID_BITMASK) {
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+ of_node_put(cpu);
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return;
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return;
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+ }
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/*
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/*
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* Duplicate MPIDRs are a recipe for disaster.
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* Duplicate MPIDRs are a recipe for disaster.
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@@ -119,9 +122,11 @@ void __init arm_dt_init_cpu_maps(void)
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* to avoid matching valid MPIDR[23:0] values.
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* to avoid matching valid MPIDR[23:0] values.
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*/
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*/
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for (j = 0; j < cpuidx; j++)
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for (j = 0; j < cpuidx; j++)
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- if (WARN(tmp_map[j] == hwid, "Duplicate /cpu reg "
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- "properties in the DT\n"))
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+ if (WARN(tmp_map[j] == hwid,
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+ "Duplicate /cpu reg properties in the DT\n")) {
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+ of_node_put(cpu);
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return;
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return;
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+ }
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/*
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/*
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* Build a stashed array of MPIDR values. Numbering scheme
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* Build a stashed array of MPIDR values. Numbering scheme
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@@ -143,6 +148,7 @@ void __init arm_dt_init_cpu_maps(void)
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"max cores %u, capping them\n",
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"max cores %u, capping them\n",
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cpuidx, nr_cpu_ids)) {
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cpuidx, nr_cpu_ids)) {
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cpuidx = nr_cpu_ids;
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cpuidx = nr_cpu_ids;
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+ of_node_put(cpu);
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break;
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break;
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}
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}
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