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@@ -217,6 +217,7 @@ static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
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{
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struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
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struct azx *chip = apcm->chip;
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+ struct hdac_bus *bus = azx_bus(chip);
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struct azx_dev *azx_dev;
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struct snd_pcm_substream *s;
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struct hdac_stream *hstr;
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@@ -257,7 +258,7 @@ static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
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snd_pcm_trigger_done(s, substream);
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}
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- spin_lock(&chip->reg_lock);
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+ spin_lock(&bus->reg_lock);
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/* first, set SYNC bits of corresponding streams */
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snd_hdac_stream_sync_trigger(hstr, true, sbits, sync_reg);
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@@ -273,16 +274,16 @@ static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
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snd_hdac_stream_stop(azx_stream(azx_dev));
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}
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}
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- spin_unlock(&chip->reg_lock);
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+ spin_unlock(&bus->reg_lock);
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snd_hdac_stream_sync(hstr, start, sbits);
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- spin_lock(&chip->reg_lock);
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+ spin_lock(&bus->reg_lock);
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/* reset SYNC bits */
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snd_hdac_stream_sync_trigger(hstr, false, sbits, sync_reg);
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if (start)
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snd_hdac_stream_timecounter_init(hstr, sbits);
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- spin_unlock(&chip->reg_lock);
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+ spin_unlock(&bus->reg_lock);
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return 0;
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}
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@@ -522,10 +523,11 @@ static void azx_pcm_free(struct snd_pcm *pcm)
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#define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
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-static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
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+static int azx_attach_pcm_stream(struct hda_bus *_bus, struct hda_codec *codec,
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struct hda_pcm *cpcm)
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{
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- struct azx *chip = bus->private_data;
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+ struct hdac_bus *bus = &_bus->core;
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+ struct azx *chip = bus_to_azx(bus);
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struct snd_pcm *pcm;
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struct azx_pcm *apcm;
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int pcm_dev = cpcm->device;
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@@ -573,89 +575,6 @@ static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
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return 0;
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}
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-/*
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- * CORB / RIRB interface
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- */
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-static int azx_alloc_cmd_io(struct azx *chip)
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-{
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- /* single page (at least 4096 bytes) must suffice for both ringbuffes */
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- return chip->io_ops->dma_alloc_pages(azx_bus(chip), SNDRV_DMA_TYPE_DEV,
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- PAGE_SIZE, &chip->rb);
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-}
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-
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-static void azx_init_cmd_io(struct azx *chip)
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-{
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- int timeout;
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-
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- spin_lock_irq(&chip->reg_lock);
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- /* CORB set up */
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- chip->corb.addr = chip->rb.addr;
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- chip->corb.buf = (u32 *)chip->rb.area;
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- azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
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- azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
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-
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- /* set the corb size to 256 entries (ULI requires explicitly) */
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- azx_writeb(chip, CORBSIZE, 0x02);
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- /* set the corb write pointer to 0 */
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- azx_writew(chip, CORBWP, 0);
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-
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- /* reset the corb hw read pointer */
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- azx_writew(chip, CORBRP, AZX_CORBRP_RST);
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- if (!(chip->driver_caps & AZX_DCAPS_CORBRP_SELF_CLEAR)) {
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- for (timeout = 1000; timeout > 0; timeout--) {
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- if ((azx_readw(chip, CORBRP) & AZX_CORBRP_RST) == AZX_CORBRP_RST)
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- break;
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- udelay(1);
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- }
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- if (timeout <= 0)
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- dev_err(chip->card->dev, "CORB reset timeout#1, CORBRP = %d\n",
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- azx_readw(chip, CORBRP));
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-
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- azx_writew(chip, CORBRP, 0);
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- for (timeout = 1000; timeout > 0; timeout--) {
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- if (azx_readw(chip, CORBRP) == 0)
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- break;
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- udelay(1);
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- }
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- if (timeout <= 0)
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- dev_err(chip->card->dev, "CORB reset timeout#2, CORBRP = %d\n",
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- azx_readw(chip, CORBRP));
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- }
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-
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- /* enable corb dma */
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- azx_writeb(chip, CORBCTL, AZX_CORBCTL_RUN);
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-
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- /* RIRB set up */
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- chip->rirb.addr = chip->rb.addr + 2048;
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- chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
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- chip->rirb.wp = chip->rirb.rp = 0;
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- memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
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- azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
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- azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
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-
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- /* set the rirb size to 256 entries (ULI requires explicitly) */
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- azx_writeb(chip, RIRBSIZE, 0x02);
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- /* reset the rirb hw write pointer */
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- azx_writew(chip, RIRBWP, AZX_RIRBWP_RST);
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- /* set N=1, get RIRB response interrupt for new entry */
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- if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
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- azx_writew(chip, RINTCNT, 0xc0);
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- else
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- azx_writew(chip, RINTCNT, 1);
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- /* enable rirb dma and response irq */
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- azx_writeb(chip, RIRBCTL, AZX_RBCTL_DMA_EN | AZX_RBCTL_IRQ_EN);
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- spin_unlock_irq(&chip->reg_lock);
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-}
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-
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-static void azx_free_cmd_io(struct azx *chip)
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-{
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- spin_lock_irq(&chip->reg_lock);
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- /* disable ringbuffer DMAs */
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- azx_writeb(chip, RIRBCTL, 0);
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- azx_writeb(chip, CORBCTL, 0);
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- spin_unlock_irq(&chip->reg_lock);
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-}
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-
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static unsigned int azx_command_addr(u32 cmd)
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{
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unsigned int addr = cmd >> 28;
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@@ -668,92 +587,12 @@ static unsigned int azx_command_addr(u32 cmd)
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return addr;
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}
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-/* send a command */
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-static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
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-{
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- struct azx *chip = bus->private_data;
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- unsigned int addr = azx_command_addr(val);
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- unsigned int wp, rp;
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-
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- spin_lock_irq(&chip->reg_lock);
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-
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- /* add command to corb */
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- wp = azx_readw(chip, CORBWP);
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- if (wp == 0xffff) {
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- /* something wrong, controller likely turned to D3 */
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- spin_unlock_irq(&chip->reg_lock);
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- return -EIO;
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- }
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- wp++;
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- wp %= AZX_MAX_CORB_ENTRIES;
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-
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- rp = azx_readw(chip, CORBRP);
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- if (wp == rp) {
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- /* oops, it's full */
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- spin_unlock_irq(&chip->reg_lock);
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- return -EAGAIN;
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- }
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-
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- chip->rirb.cmds[addr]++;
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- chip->corb.buf[wp] = cpu_to_le32(val);
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- azx_writew(chip, CORBWP, wp);
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-
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- spin_unlock_irq(&chip->reg_lock);
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-
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- return 0;
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-}
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-
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-#define AZX_RIRB_EX_UNSOL_EV (1<<4)
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-
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-/* retrieve RIRB entry - called from interrupt handler */
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-static void azx_update_rirb(struct azx *chip)
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-{
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- unsigned int rp, wp;
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- unsigned int addr;
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- u32 res, res_ex;
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-
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- wp = azx_readw(chip, RIRBWP);
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- if (wp == 0xffff) {
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- /* something wrong, controller likely turned to D3 */
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- return;
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- }
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-
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- if (wp == chip->rirb.wp)
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- return;
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- chip->rirb.wp = wp;
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-
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- while (chip->rirb.rp != wp) {
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- chip->rirb.rp++;
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- chip->rirb.rp %= AZX_MAX_RIRB_ENTRIES;
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-
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- rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
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- res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
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- res = le32_to_cpu(chip->rirb.buf[rp]);
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- addr = res_ex & 0xf;
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- if ((addr >= AZX_MAX_CODECS) || !(chip->codec_mask & (1 << addr))) {
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- dev_err(chip->card->dev, "spurious response %#x:%#x, rp = %d, wp = %d",
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- res, res_ex,
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- chip->rirb.rp, wp);
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- snd_BUG();
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- } else if (res_ex & AZX_RIRB_EX_UNSOL_EV)
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- snd_hda_queue_unsol_event(chip->bus, res, res_ex);
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- else if (chip->rirb.cmds[addr]) {
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- chip->rirb.res[addr] = res;
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- smp_wmb();
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- chip->rirb.cmds[addr]--;
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- } else if (printk_ratelimit()) {
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- dev_err(chip->card->dev, "spurious response %#x:%#x, last cmd=%#08x\n",
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- res, res_ex,
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- chip->last_cmd[addr]);
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- }
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- }
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-}
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-
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/* receive a response */
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-static int azx_rirb_get_response(struct hda_bus *bus, unsigned int addr,
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+static int azx_rirb_get_response(struct hdac_bus *bus, unsigned int addr,
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unsigned int *res)
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{
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- struct azx *chip = bus->private_data;
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+ struct azx *chip = bus_to_azx(bus);
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+ struct hda_bus *hbus = &chip->bus;
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unsigned long timeout;
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unsigned long loopcounter;
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int do_poll = 0;
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@@ -762,23 +601,21 @@ static int azx_rirb_get_response(struct hda_bus *bus, unsigned int addr,
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timeout = jiffies + msecs_to_jiffies(1000);
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for (loopcounter = 0;; loopcounter++) {
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- if (chip->polling_mode || do_poll) {
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- spin_lock_irq(&chip->reg_lock);
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- azx_update_rirb(chip);
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- spin_unlock_irq(&chip->reg_lock);
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- }
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- if (!chip->rirb.cmds[addr]) {
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- smp_rmb();
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-
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+ spin_lock_irq(&bus->reg_lock);
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+ if (chip->polling_mode || do_poll)
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+ snd_hdac_bus_update_rirb(bus);
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+ if (!bus->rirb.cmds[addr]) {
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if (!do_poll)
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chip->poll_count = 0;
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if (res)
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- *res = chip->rirb.res[addr]; /* the last value */
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+ *res = bus->rirb.res[addr]; /* the last value */
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+ spin_unlock_irq(&bus->reg_lock);
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return 0;
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}
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+ spin_unlock_irq(&bus->reg_lock);
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if (time_after(jiffies, timeout))
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break;
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- if (bus->needs_damn_long_delay || loopcounter > 3000)
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+ if (hbus->needs_damn_long_delay || loopcounter > 3000)
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msleep(2); /* temporary workaround */
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else {
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udelay(10);
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@@ -786,13 +623,13 @@ static int azx_rirb_get_response(struct hda_bus *bus, unsigned int addr,
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}
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}
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- if (bus->no_response_fallback)
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+ if (hbus->no_response_fallback)
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return -EIO;
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if (!chip->polling_mode && chip->poll_count < 2) {
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dev_dbg(chip->card->dev,
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"azx_get_response timeout, polling the codec once: last cmd=0x%08x\n",
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- chip->last_cmd[addr]);
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+ bus->last_cmd[addr]);
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do_poll = 1;
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chip->poll_count++;
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goto again;
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@@ -802,7 +639,7 @@ static int azx_rirb_get_response(struct hda_bus *bus, unsigned int addr,
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if (!chip->polling_mode) {
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dev_warn(chip->card->dev,
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"azx_get_response timeout, switching to polling mode: last cmd=0x%08x\n",
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- chip->last_cmd[addr]);
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+ bus->last_cmd[addr]);
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chip->polling_mode = 1;
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goto again;
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}
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@@ -810,8 +647,8 @@ static int azx_rirb_get_response(struct hda_bus *bus, unsigned int addr,
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if (chip->msi) {
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dev_warn(chip->card->dev,
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"No response from codec, disabling MSI: last cmd=0x%08x\n",
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- chip->last_cmd[addr]);
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- if (chip->ops->disable_msi_reset_irq(chip) &&
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+ bus->last_cmd[addr]);
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+ if (chip->ops->disable_msi_reset_irq &&
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chip->ops->disable_msi_reset_irq(chip) < 0)
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return -EIO;
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goto again;
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@@ -828,20 +665,17 @@ static int azx_rirb_get_response(struct hda_bus *bus, unsigned int addr,
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/* a fatal communication error; need either to reset or to fallback
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* to the single_cmd mode
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*/
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- if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
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- bus->response_reset = 1;
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+ if (hbus->allow_bus_reset && !hbus->response_reset && !hbus->in_reset) {
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+ hbus->response_reset = 1;
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return -EAGAIN; /* give a chance to retry */
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}
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dev_err(chip->card->dev,
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"azx_get_response timeout, switching to single_cmd mode: last cmd=0x%08x\n",
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- chip->last_cmd[addr]);
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+ bus->last_cmd[addr]);
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chip->single_cmd = 1;
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- bus->response_reset = 0;
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- /* release CORB/RIRB */
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- azx_free_cmd_io(chip);
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- /* disable unsolicited responses */
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- azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~AZX_GCTL_UNSOL);
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+ hbus->response_reset = 0;
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+ snd_hdac_bus_stop_cmd_io(bus);
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return -EIO;
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}
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@@ -864,7 +698,7 @@ static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
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/* check IRV busy bit */
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if (azx_readw(chip, IRS) & AZX_IRS_VALID) {
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/* reuse rirb.res as the response return value */
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- chip->rirb.res[addr] = azx_readl(chip, IR);
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+ azx_bus(chip)->rirb.res[addr] = azx_readl(chip, IR);
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return 0;
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}
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udelay(1);
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@@ -872,17 +706,18 @@ static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
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if (printk_ratelimit())
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dev_dbg(chip->card->dev, "get_response timeout: IRS=0x%x\n",
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azx_readw(chip, IRS));
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- chip->rirb.res[addr] = -1;
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+ azx_bus(chip)->rirb.res[addr] = -1;
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return -EIO;
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}
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/* send a command */
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-static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
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+static int azx_single_send_cmd(struct hdac_bus *bus, u32 val)
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{
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- struct azx *chip = bus->private_data;
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+ struct azx *chip = bus_to_azx(bus);
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unsigned int addr = azx_command_addr(val);
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int timeout = 50;
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+ bus->last_cmd[azx_command_addr(val)] = val;
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while (timeout--) {
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/* check ICB busy bit */
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if (!((azx_readw(chip, IRS) & AZX_IRS_BUSY))) {
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@@ -904,13 +739,11 @@ static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
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}
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/* receive a response */
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-static int azx_single_get_response(struct hda_bus *bus, unsigned int addr,
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+static int azx_single_get_response(struct hdac_bus *bus, unsigned int addr,
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unsigned int *res)
|
|
|
{
|
|
|
- struct azx *chip = bus->private_data;
|
|
|
-
|
|
|
if (res)
|
|
|
- *res = chip->rirb.res[addr];
|
|
|
+ *res = bus->rirb.res[addr];
|
|
|
return 0;
|
|
|
}
|
|
|
|
|
@@ -922,26 +755,24 @@ static int azx_single_get_response(struct hda_bus *bus, unsigned int addr,
|
|
|
*/
|
|
|
|
|
|
/* send a command */
|
|
|
-static int azx_send_cmd(struct hdac_bus *_bus, unsigned int val)
|
|
|
+static int azx_send_cmd(struct hdac_bus *bus, unsigned int val)
|
|
|
{
|
|
|
- struct hda_bus *bus = to_hda_bus(_bus);
|
|
|
- struct azx *chip = bus->private_data;
|
|
|
+ struct azx *chip = bus_to_azx(bus);
|
|
|
|
|
|
if (chip->disabled)
|
|
|
return 0;
|
|
|
- chip->last_cmd[azx_command_addr(val)] = val;
|
|
|
if (chip->single_cmd)
|
|
|
return azx_single_send_cmd(bus, val);
|
|
|
else
|
|
|
- return azx_corb_send_cmd(bus, val);
|
|
|
+ return snd_hdac_bus_send_cmd(bus, val);
|
|
|
}
|
|
|
|
|
|
/* get a response */
|
|
|
-static int azx_get_response(struct hdac_bus *_bus, unsigned int addr,
|
|
|
+static int azx_get_response(struct hdac_bus *bus, unsigned int addr,
|
|
|
unsigned int *res)
|
|
|
{
|
|
|
- struct hda_bus *bus = to_hda_bus(_bus);
|
|
|
- struct azx *chip = bus->private_data;
|
|
|
+ struct azx *chip = bus_to_azx(bus);
|
|
|
+
|
|
|
if (chip->disabled)
|
|
|
return 0;
|
|
|
if (chip->single_cmd)
|
|
@@ -974,11 +805,12 @@ azx_get_dsp_loader_dev(struct azx *chip)
|
|
|
return NULL;
|
|
|
}
|
|
|
|
|
|
-static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
|
|
|
+static int azx_load_dsp_prepare(struct hda_bus *_bus, unsigned int format,
|
|
|
unsigned int byte_size,
|
|
|
struct snd_dma_buffer *bufp)
|
|
|
{
|
|
|
- struct azx *chip = bus->private_data;
|
|
|
+ struct hdac_bus *bus = &_bus->core;
|
|
|
+ struct azx *chip = bus_to_azx(bus);
|
|
|
struct azx_dev *azx_dev;
|
|
|
struct hdac_stream *hstr;
|
|
|
bool saved = false;
|
|
@@ -986,19 +818,19 @@ static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
|
|
|
|
|
|
azx_dev = azx_get_dsp_loader_dev(chip);
|
|
|
hstr = azx_stream(azx_dev);
|
|
|
- spin_lock_irq(&chip->reg_lock);
|
|
|
+ spin_lock_irq(&bus->reg_lock);
|
|
|
if (hstr->opened) {
|
|
|
chip->saved_azx_dev = *azx_dev;
|
|
|
saved = true;
|
|
|
}
|
|
|
- spin_unlock_irq(&chip->reg_lock);
|
|
|
+ spin_unlock_irq(&bus->reg_lock);
|
|
|
|
|
|
err = snd_hdac_dsp_prepare(hstr, format, byte_size, bufp);
|
|
|
if (err < 0) {
|
|
|
- spin_lock_irq(&chip->reg_lock);
|
|
|
+ spin_lock_irq(&bus->reg_lock);
|
|
|
if (saved)
|
|
|
*azx_dev = chip->saved_azx_dev;
|
|
|
- spin_unlock_irq(&chip->reg_lock);
|
|
|
+ spin_unlock_irq(&bus->reg_lock);
|
|
|
return err;
|
|
|
}
|
|
|
|
|
@@ -1006,18 +838,20 @@ static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
|
|
|
return err;
|
|
|
}
|
|
|
|
|
|
-static void azx_load_dsp_trigger(struct hda_bus *bus, bool start)
|
|
|
+static void azx_load_dsp_trigger(struct hda_bus *_bus, bool start)
|
|
|
{
|
|
|
- struct azx *chip = bus->private_data;
|
|
|
+ struct hdac_bus *bus = &_bus->core;
|
|
|
+ struct azx *chip = bus_to_azx(bus);
|
|
|
struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
|
|
|
|
|
|
snd_hdac_dsp_trigger(azx_stream(azx_dev), start);
|
|
|
}
|
|
|
|
|
|
-static void azx_load_dsp_cleanup(struct hda_bus *bus,
|
|
|
+static void azx_load_dsp_cleanup(struct hda_bus *_bus,
|
|
|
struct snd_dma_buffer *dmab)
|
|
|
{
|
|
|
- struct azx *chip = bus->private_data;
|
|
|
+ struct hdac_bus *bus = &_bus->core;
|
|
|
+ struct azx *chip = bus_to_azx(bus);
|
|
|
struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
|
|
|
struct hdac_stream *hstr = azx_stream(azx_dev);
|
|
|
|
|
@@ -1025,207 +859,24 @@ static void azx_load_dsp_cleanup(struct hda_bus *bus,
|
|
|
return;
|
|
|
|
|
|
snd_hdac_dsp_cleanup(hstr, dmab);
|
|
|
- spin_lock_irq(&chip->reg_lock);
|
|
|
+ spin_lock_irq(&bus->reg_lock);
|
|
|
if (hstr->opened)
|
|
|
*azx_dev = chip->saved_azx_dev;
|
|
|
hstr->locked = false;
|
|
|
- spin_unlock_irq(&chip->reg_lock);
|
|
|
+ spin_unlock_irq(&bus->reg_lock);
|
|
|
}
|
|
|
#endif /* CONFIG_SND_HDA_DSP_LOADER */
|
|
|
|
|
|
-int azx_alloc_stream_pages(struct azx *chip)
|
|
|
-{
|
|
|
- struct hdac_bus *bus = azx_bus(chip);
|
|
|
- struct hdac_stream *s;
|
|
|
- int err;
|
|
|
-
|
|
|
- list_for_each_entry(s, &bus->stream_list, list) {
|
|
|
- /* allocate memory for the BDL for each stream */
|
|
|
- err = chip->io_ops->dma_alloc_pages(azx_bus(chip), SNDRV_DMA_TYPE_DEV,
|
|
|
- BDL_SIZE, &s->bdl);
|
|
|
- if (err < 0)
|
|
|
- return -ENOMEM;
|
|
|
- }
|
|
|
-
|
|
|
- /* allocate memory for the position buffer */
|
|
|
- err = chip->io_ops->dma_alloc_pages(azx_bus(chip), SNDRV_DMA_TYPE_DEV,
|
|
|
- chip->num_streams * 8, &chip->posbuf);
|
|
|
- if (err < 0)
|
|
|
- return -ENOMEM;
|
|
|
-
|
|
|
- /* allocate CORB/RIRB */
|
|
|
- err = azx_alloc_cmd_io(chip);
|
|
|
- if (err < 0)
|
|
|
- return err;
|
|
|
- return 0;
|
|
|
-}
|
|
|
-EXPORT_SYMBOL_GPL(azx_alloc_stream_pages);
|
|
|
-
|
|
|
-void azx_free_stream_pages(struct azx *chip)
|
|
|
-{
|
|
|
- struct hdac_bus *bus = azx_bus(chip);
|
|
|
- struct hdac_stream *s, *next;
|
|
|
-
|
|
|
- list_for_each_entry_safe(s, next, &bus->stream_list, list) {
|
|
|
- if (s->bdl.area)
|
|
|
- chip->io_ops->dma_free_pages(azx_bus(chip), &s->bdl);
|
|
|
- kfree(s);
|
|
|
- }
|
|
|
-
|
|
|
- if (chip->rb.area)
|
|
|
- chip->io_ops->dma_free_pages(azx_bus(chip), &chip->rb);
|
|
|
- if (chip->posbuf.area)
|
|
|
- chip->io_ops->dma_free_pages(azx_bus(chip), &chip->posbuf);
|
|
|
-}
|
|
|
-EXPORT_SYMBOL_GPL(azx_free_stream_pages);
|
|
|
-
|
|
|
-/*
|
|
|
- * Lowlevel interface
|
|
|
- */
|
|
|
-
|
|
|
-/* enter link reset */
|
|
|
-void azx_enter_link_reset(struct azx *chip)
|
|
|
-{
|
|
|
- unsigned long timeout;
|
|
|
-
|
|
|
- /* reset controller */
|
|
|
- azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~AZX_GCTL_RESET);
|
|
|
-
|
|
|
- timeout = jiffies + msecs_to_jiffies(100);
|
|
|
- while ((azx_readb(chip, GCTL) & AZX_GCTL_RESET) &&
|
|
|
- time_before(jiffies, timeout))
|
|
|
- usleep_range(500, 1000);
|
|
|
-}
|
|
|
-EXPORT_SYMBOL_GPL(azx_enter_link_reset);
|
|
|
-
|
|
|
-/* exit link reset */
|
|
|
-static void azx_exit_link_reset(struct azx *chip)
|
|
|
-{
|
|
|
- unsigned long timeout;
|
|
|
-
|
|
|
- azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | AZX_GCTL_RESET);
|
|
|
-
|
|
|
- timeout = jiffies + msecs_to_jiffies(100);
|
|
|
- while (!azx_readb(chip, GCTL) &&
|
|
|
- time_before(jiffies, timeout))
|
|
|
- usleep_range(500, 1000);
|
|
|
-}
|
|
|
-
|
|
|
-/* reset codec link */
|
|
|
-static int azx_reset(struct azx *chip, bool full_reset)
|
|
|
-{
|
|
|
- if (!full_reset)
|
|
|
- goto __skip;
|
|
|
-
|
|
|
- /* clear STATESTS */
|
|
|
- azx_writew(chip, STATESTS, STATESTS_INT_MASK);
|
|
|
-
|
|
|
- /* reset controller */
|
|
|
- azx_enter_link_reset(chip);
|
|
|
-
|
|
|
- /* delay for >= 100us for codec PLL to settle per spec
|
|
|
- * Rev 0.9 section 5.5.1
|
|
|
- */
|
|
|
- usleep_range(500, 1000);
|
|
|
-
|
|
|
- /* Bring controller out of reset */
|
|
|
- azx_exit_link_reset(chip);
|
|
|
-
|
|
|
- /* Brent Chartrand said to wait >= 540us for codecs to initialize */
|
|
|
- usleep_range(1000, 1200);
|
|
|
-
|
|
|
- __skip:
|
|
|
- /* check to see if controller is ready */
|
|
|
- if (!azx_readb(chip, GCTL)) {
|
|
|
- dev_dbg(chip->card->dev, "azx_reset: controller not ready!\n");
|
|
|
- return -EBUSY;
|
|
|
- }
|
|
|
-
|
|
|
- /* Accept unsolicited responses */
|
|
|
- if (!chip->single_cmd)
|
|
|
- azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
|
|
|
- AZX_GCTL_UNSOL);
|
|
|
-
|
|
|
- /* detect codecs */
|
|
|
- if (!chip->codec_mask) {
|
|
|
- chip->codec_mask = azx_readw(chip, STATESTS);
|
|
|
- dev_dbg(chip->card->dev, "codec_mask = 0x%x\n",
|
|
|
- chip->codec_mask);
|
|
|
- }
|
|
|
-
|
|
|
- return 0;
|
|
|
-}
|
|
|
-
|
|
|
-/* enable interrupts */
|
|
|
-static void azx_int_enable(struct azx *chip)
|
|
|
-{
|
|
|
- /* enable controller CIE and GIE */
|
|
|
- azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
|
|
|
- AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN);
|
|
|
-}
|
|
|
-
|
|
|
-/* disable interrupts */
|
|
|
-static void azx_int_disable(struct azx *chip)
|
|
|
-{
|
|
|
- struct hdac_bus *bus = azx_bus(chip);
|
|
|
- struct hdac_stream *s;
|
|
|
-
|
|
|
- /* disable interrupts in stream descriptor */
|
|
|
- list_for_each_entry(s, &bus->stream_list, list)
|
|
|
- snd_hdac_stream_updateb(s, SD_CTL, SD_INT_MASK, 0);
|
|
|
-
|
|
|
- /* disable SIE for all streams */
|
|
|
- azx_writeb(chip, INTCTL, 0);
|
|
|
-
|
|
|
- /* disable controller CIE and GIE */
|
|
|
- azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
|
|
|
- ~(AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN));
|
|
|
-}
|
|
|
-
|
|
|
-/* clear interrupts */
|
|
|
-static void azx_int_clear(struct azx *chip)
|
|
|
-{
|
|
|
- struct hdac_bus *bus = azx_bus(chip);
|
|
|
- struct hdac_stream *s;
|
|
|
-
|
|
|
- /* clear stream status */
|
|
|
- list_for_each_entry(s, &bus->stream_list, list)
|
|
|
- snd_hdac_stream_writeb(s, SD_STS, SD_INT_MASK);
|
|
|
-
|
|
|
- /* clear STATESTS */
|
|
|
- azx_writew(chip, STATESTS, STATESTS_INT_MASK);
|
|
|
-
|
|
|
- /* clear rirb status */
|
|
|
- azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
|
|
|
-
|
|
|
- /* clear int status */
|
|
|
- azx_writel(chip, INTSTS, AZX_INT_CTRL_EN | AZX_INT_ALL_STREAM);
|
|
|
-}
|
|
|
-
|
|
|
/*
|
|
|
* reset and start the controller registers
|
|
|
*/
|
|
|
void azx_init_chip(struct azx *chip, bool full_reset)
|
|
|
{
|
|
|
- if (chip->initialized)
|
|
|
- return;
|
|
|
-
|
|
|
- /* reset controller */
|
|
|
- azx_reset(chip, full_reset);
|
|
|
-
|
|
|
- /* initialize interrupts */
|
|
|
- azx_int_clear(chip);
|
|
|
- azx_int_enable(chip);
|
|
|
-
|
|
|
- /* initialize the codec command I/O */
|
|
|
- if (!chip->single_cmd)
|
|
|
- azx_init_cmd_io(chip);
|
|
|
-
|
|
|
- /* program the position buffer */
|
|
|
- azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
|
|
|
- azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
|
|
|
-
|
|
|
- chip->initialized = 1;
|
|
|
+ if (snd_hdac_bus_init_chip(azx_bus(chip), full_reset)) {
|
|
|
+ /* correct RINTCNT for CXT */
|
|
|
+ if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
|
|
|
+ azx_writew(chip, RINTCNT, 0xc0);
|
|
|
+ }
|
|
|
}
|
|
|
EXPORT_SYMBOL_GPL(azx_init_chip);
|
|
|
|
|
@@ -1241,21 +892,7 @@ EXPORT_SYMBOL_GPL(azx_stop_all_streams);
|
|
|
|
|
|
void azx_stop_chip(struct azx *chip)
|
|
|
{
|
|
|
- if (!chip->initialized)
|
|
|
- return;
|
|
|
-
|
|
|
- /* disable interrupts */
|
|
|
- azx_int_disable(chip);
|
|
|
- azx_int_clear(chip);
|
|
|
-
|
|
|
- /* disable CORB/RIRB */
|
|
|
- azx_free_cmd_io(chip);
|
|
|
-
|
|
|
- /* disable position buffer */
|
|
|
- azx_writel(chip, DPLBASE, 0);
|
|
|
- azx_writel(chip, DPUBASE, 0);
|
|
|
-
|
|
|
- chip->initialized = 0;
|
|
|
+ snd_hdac_bus_stop_chip(azx_bus(chip));
|
|
|
}
|
|
|
EXPORT_SYMBOL_GPL(azx_stop_chip);
|
|
|
|
|
@@ -1264,16 +901,15 @@ EXPORT_SYMBOL_GPL(azx_stop_chip);
|
|
|
*/
|
|
|
static void stream_update(struct hdac_bus *bus, struct hdac_stream *s)
|
|
|
{
|
|
|
- struct hda_bus *hbus = container_of(bus, struct hda_bus, core);
|
|
|
- struct azx *chip = hbus->private_data;
|
|
|
+ struct azx *chip = bus_to_azx(bus);
|
|
|
struct azx_dev *azx_dev = stream_to_azx_dev(s);
|
|
|
|
|
|
/* check whether this IRQ is really acceptable */
|
|
|
if (!chip->ops->position_check ||
|
|
|
chip->ops->position_check(chip, azx_dev)) {
|
|
|
- spin_unlock(&chip->reg_lock);
|
|
|
- snd_pcm_period_elapsed(azx_dev->core.substream);
|
|
|
- spin_lock(&chip->reg_lock);
|
|
|
+ spin_unlock(&bus->reg_lock);
|
|
|
+ snd_pcm_period_elapsed(azx_stream(azx_dev)->substream);
|
|
|
+ spin_lock(&bus->reg_lock);
|
|
|
}
|
|
|
}
|
|
|
|
|
@@ -1289,16 +925,16 @@ irqreturn_t azx_interrupt(int irq, void *dev_id)
|
|
|
return IRQ_NONE;
|
|
|
#endif
|
|
|
|
|
|
- spin_lock(&chip->reg_lock);
|
|
|
+ spin_lock(&bus->reg_lock);
|
|
|
|
|
|
if (chip->disabled) {
|
|
|
- spin_unlock(&chip->reg_lock);
|
|
|
+ spin_unlock(&bus->reg_lock);
|
|
|
return IRQ_NONE;
|
|
|
}
|
|
|
|
|
|
status = azx_readl(chip, INTSTS);
|
|
|
if (status == 0 || status == 0xffffffff) {
|
|
|
- spin_unlock(&chip->reg_lock);
|
|
|
+ spin_unlock(&bus->reg_lock);
|
|
|
return IRQ_NONE;
|
|
|
}
|
|
|
|
|
@@ -1310,12 +946,12 @@ irqreturn_t azx_interrupt(int irq, void *dev_id)
|
|
|
if (status & RIRB_INT_RESPONSE) {
|
|
|
if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
|
|
|
udelay(80);
|
|
|
- azx_update_rirb(chip);
|
|
|
+ snd_hdac_bus_update_rirb(bus);
|
|
|
}
|
|
|
azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
|
|
|
}
|
|
|
|
|
|
- spin_unlock(&chip->reg_lock);
|
|
|
+ spin_unlock(&bus->reg_lock);
|
|
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return IRQ_HANDLED;
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}
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@@ -1334,7 +970,7 @@ static int probe_codec(struct azx *chip, int addr)
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(AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
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struct hdac_bus *bus = azx_bus(chip);
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int err;
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- unsigned int res;
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+ unsigned int res = -1;
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mutex_lock(&bus->cmd_mutex);
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chip->probing = 1;
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@@ -1350,13 +986,13 @@ static int probe_codec(struct azx *chip, int addr)
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static void azx_bus_reset(struct hda_bus *bus)
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{
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- struct azx *chip = bus->private_data;
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+ struct azx *chip = bus_to_azx(&bus->core);
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bus->in_reset = 1;
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azx_stop_chip(chip);
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azx_init_chip(chip, true);
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- if (chip->initialized)
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- snd_hda_bus_reset(chip->bus);
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+ if (bus->core.chip_init)
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+ snd_hda_bus_reset(bus);
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bus->in_reset = 0;
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}
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@@ -1392,17 +1028,19 @@ static struct hda_bus_ops bus_ops = {
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};
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/* HD-audio bus initialization */
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-int azx_bus_create(struct azx *chip, const char *model)
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+int azx_bus_init(struct azx *chip, const char *model,
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+ const struct hdac_io_ops *io_ops)
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{
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- struct hda_bus *bus;
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+ struct hda_bus *bus = &chip->bus;
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int err;
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- err = snd_hda_bus_new(chip->card, &bus_core_ops, chip->io_ops, &bus);
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+ err = snd_hdac_bus_init(&bus->core, chip->card->dev, &bus_core_ops,
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+ io_ops);
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if (err < 0)
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return err;
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- chip->bus = bus;
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- bus->private_data = chip;
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+ bus->card = chip->card;
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+ mutex_init(&bus->prepare_mutex);
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bus->pci = chip->pci;
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bus->modelname = model;
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bus->ops = bus_ops;
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@@ -1412,6 +1050,8 @@ int azx_bus_create(struct azx *chip, const char *model)
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bus->core.use_posbuf = true;
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if (chip->bdl_pos_adj)
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bus->core.bdl_pos_adj = chip->bdl_pos_adj[chip->dev_index];
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+ if (chip->driver_caps & AZX_DCAPS_CORBRP_SELF_CLEAR)
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+ bus->core.corbrp_self_clear = true;
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if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
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dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
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@@ -1430,12 +1070,12 @@ int azx_bus_create(struct azx *chip, const char *model)
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return 0;
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}
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-EXPORT_SYMBOL_GPL(azx_bus_create);
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+EXPORT_SYMBOL_GPL(azx_bus_init);
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/* Probe codecs */
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int azx_probe_codecs(struct azx *chip, unsigned int max_slots)
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{
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- struct hda_bus *bus = chip->bus;
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+ struct hdac_bus *bus = azx_bus(chip);
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int c, codecs, err;
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codecs = 0;
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@@ -1444,14 +1084,14 @@ int azx_probe_codecs(struct azx *chip, unsigned int max_slots)
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/* First try to probe all given codec slots */
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for (c = 0; c < max_slots; c++) {
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- if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
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+ if ((bus->codec_mask & (1 << c)) & chip->codec_probe_mask) {
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if (probe_codec(chip, c) < 0) {
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/* Some BIOSen give you wrong codec addresses
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* that don't exist
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*/
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dev_warn(chip->card->dev,
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"Codec #%d probe error; disabling it...\n", c);
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- chip->codec_mask &= ~(1 << c);
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+ bus->codec_mask &= ~(1 << c);
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/* More badly, accessing to a non-existing
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* codec often screws up the controller chip,
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* and disturbs the further communications.
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@@ -1467,9 +1107,9 @@ int azx_probe_codecs(struct azx *chip, unsigned int max_slots)
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/* Then create codec instances */
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for (c = 0; c < max_slots; c++) {
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- if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
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+ if ((bus->codec_mask & (1 << c)) & chip->codec_probe_mask) {
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struct hda_codec *codec;
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- err = snd_hda_codec_new(bus, bus->card, c, &codec);
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+ err = snd_hda_codec_new(&chip->bus, chip->card, c, &codec);
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if (err < 0)
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|
continue;
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|
codec->jackpoll_interval = get_jackpoll_interval(chip);
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|
@@ -1489,7 +1129,7 @@ EXPORT_SYMBOL_GPL(azx_probe_codecs);
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|
int azx_codec_configure(struct azx *chip)
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|
|
{
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|
|
struct hda_codec *codec;
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|
- list_for_each_codec(codec, chip->bus) {
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|
+ list_for_each_codec(codec, &chip->bus) {
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|
snd_hda_codec_configure(codec);
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|
}
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|
return 0;
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|
@@ -1505,7 +1145,7 @@ static int stream_direction(struct azx *chip, unsigned char index)
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|
}
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|
|
/* initialize SD streams */
|
|
|
-int azx_init_stream(struct azx *chip)
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|
|
+int azx_init_streams(struct azx *chip)
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|
|
{
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|
|
int i;
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|
|
int stream_tags[2] = { 0, 0 };
|
|
@@ -1538,4 +1178,17 @@ int azx_init_stream(struct azx *chip)
|
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|
|
|
|
return 0;
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|
|
}
|
|
|
-EXPORT_SYMBOL_GPL(azx_init_stream);
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|
|
+EXPORT_SYMBOL_GPL(azx_init_streams);
|
|
|
+
|
|
|
+void azx_free_streams(struct azx *chip)
|
|
|
+{
|
|
|
+ struct hdac_bus *bus = azx_bus(chip);
|
|
|
+ struct hdac_stream *s;
|
|
|
+
|
|
|
+ while (!list_empty(&bus->stream_list)) {
|
|
|
+ s = list_first_entry(&bus->stream_list, struct hdac_stream, list);
|
|
|
+ list_del(&s->list);
|
|
|
+ kfree(stream_to_azx_dev(s));
|
|
|
+ }
|
|
|
+}
|
|
|
+EXPORT_SYMBOL_GPL(azx_free_streams);
|