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@@ -197,6 +197,9 @@ FEXPORT(nlm_reset_entry)
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EXPORT(nlm_boot_siblings)
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/* core L1D flush before enable threads */
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xlp_flush_l1_dcache
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+ /* save ra and sp, will be used later (only for boot cpu) */
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+ dmtc0 ra, $22, 6
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+ dmtc0 sp, $22, 7
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/* Enable hw threads by writing to MAP_THREADMODE of the core */
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li t0, CKSEG1ADDR(RESET_DATA_PHYS)
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lw t1, BOOT_THREAD_MODE(t0) /* t1 <- thread mode */
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@@ -238,14 +241,12 @@ EXPORT(nlm_boot_siblings)
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nop
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/*
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- * For the boot CPU, we have to restore registers and
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- * return
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+ * For the boot CPU, we have to restore ra and sp and return, rest
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+ * of the registers will be restored by the caller
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*/
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-4: dmfc0 t0, $4, 2 /* restore SP from UserLocal */
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- li t1, 0xfadebeef
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- dmtc0 t1, $4, 2 /* restore SP from UserLocal */
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- PTR_SUBU sp, t0, PT_SIZE
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- RESTORE_ALL
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+4:
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+ dmfc0 ra, $22, 6
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+ dmfc0 sp, $22, 7
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jr ra
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nop
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EXPORT(nlm_reset_entry_end)
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