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@@ -1168,16 +1168,9 @@ static int sunxi_nand_ecc_init(struct mtd_info *mtd, struct nand_ecc_ctrl *ecc,
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struct device_node *np)
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{
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struct nand_chip *nand = mtd->priv;
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- int strength;
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- int blk_size;
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int ret;
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- blk_size = of_get_nand_ecc_step_size(np);
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- strength = of_get_nand_ecc_strength(np);
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- if (blk_size > 0 && strength > 0) {
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- ecc->size = blk_size;
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- ecc->strength = strength;
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- } else {
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+ if (!ecc->size) {
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ecc->size = nand->ecc_step_ds;
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ecc->strength = nand->ecc_strength_ds;
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}
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@@ -1185,12 +1178,6 @@ static int sunxi_nand_ecc_init(struct mtd_info *mtd, struct nand_ecc_ctrl *ecc,
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if (!ecc->size || !ecc->strength)
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return -EINVAL;
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- ecc->mode = NAND_ECC_HW;
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-
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- ret = of_get_nand_ecc_mode(np);
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- if (ret >= 0)
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- ecc->mode = ret;
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-
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switch (ecc->mode) {
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case NAND_ECC_SOFT_BCH:
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break;
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@@ -1316,15 +1303,18 @@ static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc,
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/* Default tR value specified in the ONFI spec (chapter 4.15.1) */
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nand->chip_delay = 200;
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nand->controller = &nfc->controller;
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+ /*
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+ * Set the ECC mode to the default value in case nothing is specified
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+ * in the DT.
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+ */
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+ nand->ecc.mode = NAND_ECC_HW;
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+ nand->flash_node = np;
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nand->select_chip = sunxi_nfc_select_chip;
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nand->cmd_ctrl = sunxi_nfc_cmd_ctrl;
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nand->read_buf = sunxi_nfc_read_buf;
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nand->write_buf = sunxi_nfc_write_buf;
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nand->read_byte = sunxi_nfc_read_byte;
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- if (of_get_nand_on_flash_bbt(np))
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- nand->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
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-
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mtd = &chip->mtd;
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mtd->dev.parent = dev;
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mtd->priv = nand;
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@@ -1334,6 +1324,9 @@ static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc,
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if (ret)
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return ret;
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+ if (nand->bbt_options & NAND_BBT_USE_FLASH)
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+ nand->bbt_options |= NAND_BBT_NO_OOB;
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+
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ret = sunxi_nand_chip_init_timings(chip, np);
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if (ret) {
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dev_err(dev, "could not configure chip timings: %d\n", ret);
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