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@@ -138,7 +138,7 @@ static void mmhub_v1_0_init_tlb_regs(struct amdgpu_device *adev)
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static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
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{
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- uint32_t tmp, field;
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+ uint32_t tmp;
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/* Setup L2 cache */
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tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL);
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@@ -157,9 +157,8 @@ static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
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tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
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WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2, tmp);
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- field = adev->vm_manager.fragment_size;
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tmp = mmVM_L2_CNTL3_DEFAULT;
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- tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
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+ tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
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tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
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WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, tmp);
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