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@@ -889,6 +889,15 @@ static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
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SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
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SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
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}
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}
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+static void sdma_v2_4_ring_emit_wreg(struct amdgpu_ring *ring,
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+ uint32_t reg, uint32_t val)
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+{
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+ amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
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+ SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
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+ amdgpu_ring_write(ring, reg);
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+ amdgpu_ring_write(ring, val);
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+}
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+
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static int sdma_v2_4_early_init(void *handle)
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static int sdma_v2_4_early_init(void *handle)
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{
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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@@ -1219,6 +1228,7 @@ static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
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.test_ib = sdma_v2_4_ring_test_ib,
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.test_ib = sdma_v2_4_ring_test_ib,
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.insert_nop = sdma_v2_4_ring_insert_nop,
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.insert_nop = sdma_v2_4_ring_insert_nop,
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.pad_ib = sdma_v2_4_ring_pad_ib,
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.pad_ib = sdma_v2_4_ring_pad_ib,
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+ .emit_wreg = sdma_v2_4_ring_emit_wreg,
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};
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};
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static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev)
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static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev)
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