ARM: OMAP4+: PM: Program CPU logic power state

CPU logic power state is never programmed in either the initialization
or the suspend/resume logic, instead, we depend on mpuss to program this
properly. However, this leaves CPU logic power state indeterminate and
most probably in reset configuration (If bootloader or other similar
software have'nt monkeyed with the register). This can make powerstate=
RET be either programmed for CSWR (logic=ret) or OSWR(logic = OFF) and
in OSWR, there can be context loss when the code does not expect it.

To prevent all these confusions, just support clearly ON, INA, CSWR,
OFF which is the intent of the existing code by explicitly programming
logic state.

NOTE: since this is a hot path (using in cpuidle), the exit path just
programs powerstate (logic state is immaterial when powerstate is ON).

Without doing this, we end up with lockups when CPUs enter OSWR and
multiple blocks loose context, when we expect them to hit CSWR.

Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>

arch/arm/mach-omap2/omap-mpuss-lowpower.c

@@ -227,7 +227,7 @@ static void __init save_l2x0_context(void)
 int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
 {
 	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);
-	unsigned int save_state = 0;
+	unsigned int save_state = 0, cpu_logic_state = PWRDM_POWER_RET;
 	unsigned int wakeup_cpu;
 
 	if (omap_rev() == OMAP4430_REV_ES1_0)
@@ -239,6 +239,7 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
 		save_state = 0;
 		break;
 	case PWRDM_POWER_OFF:
+		cpu_logic_state = PWRDM_POWER_OFF;
 		save_state = 1;
 		break;
 	case PWRDM_POWER_RET:
@@ -270,6 +271,7 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
 
 	cpu_clear_prev_logic_pwrst(cpu);
 	pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
+	pwrdm_set_logic_retst(pm_info->pwrdm, cpu_logic_state);
 	set_cpu_wakeup_addr(cpu, virt_to_phys(omap_pm_ops.resume));
 	omap_pm_ops.scu_prepare(cpu, power_state);
 	l2x0_pwrst_prepare(cpu, save_state);