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@@ -3,6 +3,7 @@
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*
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* Copyright (c) 2017 MediaTek Inc.
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* Author: Ryder Lee <ryder.lee@mediatek.com>
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+ * Honghui Zhang <honghui.zhang@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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@@ -16,6 +17,9 @@
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#include <linux/clk.h>
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#include <linux/delay.h>
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+#include <linux/iopoll.h>
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+#include <linux/irq.h>
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+#include <linux/irqdomain.h>
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#include <linux/kernel.h>
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#include <linux/of_address.h>
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#include <linux/of_pci.h>
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@@ -63,16 +67,104 @@
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#define PCIE_FC_CREDIT_MASK (GENMASK(31, 31) | GENMASK(28, 16))
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#define PCIE_FC_CREDIT_VAL(x) ((x) << 16)
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+/* PCIe V2 share registers */
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+#define PCIE_SYS_CFG_V2 0x0
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+#define PCIE_CSR_LTSSM_EN(x) BIT(0 + (x) * 8)
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+#define PCIE_CSR_ASPM_L1_EN(x) BIT(1 + (x) * 8)
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+
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+/* PCIe V2 per-port registers */
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+#define PCIE_MSI_VECTOR 0x0c0
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+#define PCIE_INT_MASK 0x420
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+#define INTX_MASK GENMASK(19, 16)
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+#define INTX_SHIFT 16
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+#define PCIE_INT_STATUS 0x424
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+#define MSI_STATUS BIT(23)
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+#define PCIE_IMSI_STATUS 0x42c
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+#define PCIE_IMSI_ADDR 0x430
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+#define MSI_MASK BIT(23)
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+#define MTK_MSI_IRQS_NUM 32
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+
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+#define PCIE_AHB_TRANS_BASE0_L 0x438
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+#define PCIE_AHB_TRANS_BASE0_H 0x43c
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+#define AHB2PCIE_SIZE(x) ((x) & GENMASK(4, 0))
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+#define PCIE_AXI_WINDOW0 0x448
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+#define WIN_ENABLE BIT(7)
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+
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+/* PCIe V2 configuration transaction header */
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+#define PCIE_CFG_HEADER0 0x460
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+#define PCIE_CFG_HEADER1 0x464
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+#define PCIE_CFG_HEADER2 0x468
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+#define PCIE_CFG_WDATA 0x470
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+#define PCIE_APP_TLP_REQ 0x488
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+#define PCIE_CFG_RDATA 0x48c
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+#define APP_CFG_REQ BIT(0)
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+#define APP_CPL_STATUS GENMASK(7, 5)
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+
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+#define CFG_WRRD_TYPE_0 4
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+#define CFG_WR_FMT 2
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+#define CFG_RD_FMT 0
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+
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+#define CFG_DW0_LENGTH(length) ((length) & GENMASK(9, 0))
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+#define CFG_DW0_TYPE(type) (((type) << 24) & GENMASK(28, 24))
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+#define CFG_DW0_FMT(fmt) (((fmt) << 29) & GENMASK(31, 29))
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+#define CFG_DW2_REGN(regn) ((regn) & GENMASK(11, 2))
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+#define CFG_DW2_FUN(fun) (((fun) << 16) & GENMASK(18, 16))
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+#define CFG_DW2_DEV(dev) (((dev) << 19) & GENMASK(23, 19))
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+#define CFG_DW2_BUS(bus) (((bus) << 24) & GENMASK(31, 24))
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+#define CFG_HEADER_DW0(type, fmt) \
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+ (CFG_DW0_LENGTH(1) | CFG_DW0_TYPE(type) | CFG_DW0_FMT(fmt))
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+#define CFG_HEADER_DW1(where, size) \
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+ (GENMASK(((size) - 1), 0) << ((where) & 0x3))
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+#define CFG_HEADER_DW2(regn, fun, dev, bus) \
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+ (CFG_DW2_REGN(regn) | CFG_DW2_FUN(fun) | \
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+ CFG_DW2_DEV(dev) | CFG_DW2_BUS(bus))
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+
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+#define PCIE_RST_CTRL 0x510
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+#define PCIE_PHY_RSTB BIT(0)
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+#define PCIE_PIPE_SRSTB BIT(1)
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+#define PCIE_MAC_SRSTB BIT(2)
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+#define PCIE_CRSTB BIT(3)
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+#define PCIE_PERSTB BIT(8)
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+#define PCIE_LINKDOWN_RST_EN GENMASK(15, 13)
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+#define PCIE_LINK_STATUS_V2 0x804
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+#define PCIE_PORT_LINKUP_V2 BIT(10)
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+
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+struct mtk_pcie_port;
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+
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+/**
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+ * struct mtk_pcie_soc - differentiate between host generations
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+ * @has_msi: whether this host supports MSI interrupts or not
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+ * @ops: pointer to configuration access functions
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+ * @startup: pointer to controller setting functions
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+ * @setup_irq: pointer to initialize IRQ functions
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+ */
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+struct mtk_pcie_soc {
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+ bool has_msi;
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+ struct pci_ops *ops;
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+ int (*startup)(struct mtk_pcie_port *port);
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+ int (*setup_irq)(struct mtk_pcie_port *port, struct device_node *node);
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+};
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+
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/**
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* struct mtk_pcie_port - PCIe port information
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* @base: IO mapped register base
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* @list: port list
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* @pcie: pointer to PCIe host info
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* @reset: pointer to port reset control
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- * @sys_ck: pointer to bus clock
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- * @phy: pointer to phy control block
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+ * @sys_ck: pointer to transaction/data link layer clock
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+ * @ahb_ck: pointer to AHB slave interface operating clock for CSR access
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+ * and RC initiated MMIO access
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+ * @axi_ck: pointer to application layer MMIO channel operating clock
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+ * @aux_ck: pointer to pe2_mac_bridge and pe2_mac_core operating clock
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+ * when pcie_mac_ck/pcie_pipe_ck is turned off
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+ * @obff_ck: pointer to OBFF functional block operating clock
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+ * @pipe_ck: pointer to LTSSM and PHY/MAC layer operating clock
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+ * @phy: pointer to PHY control block
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* @lane: lane count
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- * @index: port index
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+ * @slot: port slot
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+ * @irq_domain: legacy INTx IRQ domain
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+ * @msi_domain: MSI IRQ domain
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+ * @msi_irq_in_use: bit map for assigned MSI IRQ
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*/
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struct mtk_pcie_port {
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void __iomem *base;
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@@ -80,9 +172,17 @@ struct mtk_pcie_port {
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struct mtk_pcie *pcie;
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struct reset_control *reset;
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struct clk *sys_ck;
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+ struct clk *ahb_ck;
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+ struct clk *axi_ck;
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+ struct clk *aux_ck;
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+ struct clk *obff_ck;
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+ struct clk *pipe_ck;
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struct phy *phy;
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u32 lane;
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- u32 index;
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+ u32 slot;
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+ struct irq_domain *irq_domain;
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+ struct irq_domain *msi_domain;
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+ DECLARE_BITMAP(msi_irq_in_use, MTK_MSI_IRQS_NUM);
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};
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/**
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@@ -96,6 +196,7 @@ struct mtk_pcie_port {
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* @busn: bus range
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* @offset: IO / Memory offset
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* @ports: pointer to PCIe port information
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+ * @soc: pointer to SoC-dependent operations
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*/
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struct mtk_pcie {
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struct device *dev;
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@@ -111,13 +212,9 @@ struct mtk_pcie {
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resource_size_t io;
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} offset;
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struct list_head ports;
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+ const struct mtk_pcie_soc *soc;
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};
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-static inline bool mtk_pcie_link_up(struct mtk_pcie_port *port)
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-{
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- return !!(readl(port->base + PCIE_LINK_STATUS) & PCIE_PORT_LINKUP);
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-}
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-
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static void mtk_pcie_subsys_powerdown(struct mtk_pcie *pcie)
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{
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struct device *dev = pcie->dev;
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@@ -146,6 +243,12 @@ static void mtk_pcie_put_resources(struct mtk_pcie *pcie)
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list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
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phy_power_off(port->phy);
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+ phy_exit(port->phy);
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+ clk_disable_unprepare(port->pipe_ck);
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+ clk_disable_unprepare(port->obff_ck);
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+ clk_disable_unprepare(port->axi_ck);
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+ clk_disable_unprepare(port->aux_ck);
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+ clk_disable_unprepare(port->ahb_ck);
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clk_disable_unprepare(port->sys_ck);
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mtk_pcie_port_free(port);
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}
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@@ -153,11 +256,412 @@ static void mtk_pcie_put_resources(struct mtk_pcie *pcie)
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mtk_pcie_subsys_powerdown(pcie);
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}
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+static int mtk_pcie_check_cfg_cpld(struct mtk_pcie_port *port)
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+{
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+ u32 val;
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+ int err;
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+
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+ err = readl_poll_timeout_atomic(port->base + PCIE_APP_TLP_REQ, val,
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+ !(val & APP_CFG_REQ), 10,
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+ 100 * USEC_PER_MSEC);
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+ if (err)
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+ return PCIBIOS_SET_FAILED;
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+
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+ if (readl(port->base + PCIE_APP_TLP_REQ) & APP_CPL_STATUS)
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+ return PCIBIOS_SET_FAILED;
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+
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+ return PCIBIOS_SUCCESSFUL;
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+}
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+
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+static int mtk_pcie_hw_rd_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn,
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+ int where, int size, u32 *val)
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+{
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+ u32 tmp;
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+
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+ /* Write PCIe configuration transaction header for Cfgrd */
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+ writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_RD_FMT),
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+ port->base + PCIE_CFG_HEADER0);
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+ writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
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+ writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus),
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+ port->base + PCIE_CFG_HEADER2);
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+
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+ /* Trigger h/w to transmit Cfgrd TLP */
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+ tmp = readl(port->base + PCIE_APP_TLP_REQ);
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+ tmp |= APP_CFG_REQ;
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+ writel(tmp, port->base + PCIE_APP_TLP_REQ);
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+
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+ /* Check completion status */
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+ if (mtk_pcie_check_cfg_cpld(port))
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+ return PCIBIOS_SET_FAILED;
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+
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+ /* Read cpld payload of Cfgrd */
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+ *val = readl(port->base + PCIE_CFG_RDATA);
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+
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+ if (size == 1)
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+ *val = (*val >> (8 * (where & 3))) & 0xff;
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+ else if (size == 2)
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+ *val = (*val >> (8 * (where & 3))) & 0xffff;
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+
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+ return PCIBIOS_SUCCESSFUL;
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+}
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+
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+static int mtk_pcie_hw_wr_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn,
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+ int where, int size, u32 val)
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+{
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+ /* Write PCIe configuration transaction header for Cfgwr */
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+ writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_WR_FMT),
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+ port->base + PCIE_CFG_HEADER0);
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+ writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
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+ writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus),
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+ port->base + PCIE_CFG_HEADER2);
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+
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+ /* Write Cfgwr data */
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+ val = val << 8 * (where & 3);
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+ writel(val, port->base + PCIE_CFG_WDATA);
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+
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+ /* Trigger h/w to transmit Cfgwr TLP */
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+ val = readl(port->base + PCIE_APP_TLP_REQ);
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+ val |= APP_CFG_REQ;
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+ writel(val, port->base + PCIE_APP_TLP_REQ);
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+
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+ /* Check completion status */
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+ return mtk_pcie_check_cfg_cpld(port);
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+}
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+
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+static struct mtk_pcie_port *mtk_pcie_find_port(struct pci_bus *bus,
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+ unsigned int devfn)
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+{
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+ struct mtk_pcie *pcie = bus->sysdata;
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+ struct mtk_pcie_port *port;
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+
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+ list_for_each_entry(port, &pcie->ports, list)
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+ if (port->slot == PCI_SLOT(devfn))
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+ return port;
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+
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+ return NULL;
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+}
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+
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+static int mtk_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
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+ int where, int size, u32 *val)
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+{
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+ struct mtk_pcie_port *port;
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+ u32 bn = bus->number;
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+ int ret;
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+
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+ port = mtk_pcie_find_port(bus, devfn);
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+ if (!port) {
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+ *val = ~0;
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+ return PCIBIOS_DEVICE_NOT_FOUND;
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+ }
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+
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+ ret = mtk_pcie_hw_rd_cfg(port, bn, devfn, where, size, val);
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+ if (ret)
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+ *val = ~0;
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+
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+ return ret;
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+}
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+
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+static int mtk_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
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+ int where, int size, u32 val)
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+{
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+ struct mtk_pcie_port *port;
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+ u32 bn = bus->number;
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+
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+ port = mtk_pcie_find_port(bus, devfn);
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+ if (!port)
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+ return PCIBIOS_DEVICE_NOT_FOUND;
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+
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+ return mtk_pcie_hw_wr_cfg(port, bn, devfn, where, size, val);
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+}
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+
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+static struct pci_ops mtk_pcie_ops_v2 = {
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+ .read = mtk_pcie_config_read,
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+ .write = mtk_pcie_config_write,
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+};
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+
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+static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
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+{
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+ struct mtk_pcie *pcie = port->pcie;
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+ struct resource *mem = &pcie->mem;
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+ u32 val;
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+ size_t size;
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+ int err;
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+
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+ /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */
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+ if (pcie->base) {
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+ val = readl(pcie->base + PCIE_SYS_CFG_V2);
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+ val |= PCIE_CSR_LTSSM_EN(port->slot) |
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+ PCIE_CSR_ASPM_L1_EN(port->slot);
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+ writel(val, pcie->base + PCIE_SYS_CFG_V2);
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+ }
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+
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+ /* Assert all reset signals */
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+ writel(0, port->base + PCIE_RST_CTRL);
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+
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+ /*
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+ * Enable PCIe link down reset, if link status changed from link up to
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+ * link down, this will reset MAC control registers and configuration
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+ * space.
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+ */
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+ writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
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+
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+ /* De-assert PHY, PE, PIPE, MAC and configuration reset */
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+ val = readl(port->base + PCIE_RST_CTRL);
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+ val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
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+ PCIE_MAC_SRSTB | PCIE_CRSTB;
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+ writel(val, port->base + PCIE_RST_CTRL);
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+
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+ /* 100ms timeout value should be enough for Gen1/2 training */
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+ err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val,
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+ !!(val & PCIE_PORT_LINKUP_V2), 20,
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+ 100 * USEC_PER_MSEC);
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+ if (err)
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+ return -ETIMEDOUT;
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+
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+ /* Set INTx mask */
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+ val = readl(port->base + PCIE_INT_MASK);
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+ val &= ~INTX_MASK;
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+ writel(val, port->base + PCIE_INT_MASK);
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+
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+ /* Set AHB to PCIe translation windows */
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+ size = mem->end - mem->start;
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+ val = lower_32_bits(mem->start) | AHB2PCIE_SIZE(fls(size));
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+ writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
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+
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+ val = upper_32_bits(mem->start);
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+ writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
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+
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+ /* Set PCIe to AXI translation memory space.*/
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+ val = fls(0xffffffff) | WIN_ENABLE;
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+ writel(val, port->base + PCIE_AXI_WINDOW0);
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+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static int mtk_pcie_msi_alloc(struct mtk_pcie_port *port)
|
|
|
+{
|
|
|
+ int msi;
|
|
|
+
|
|
|
+ msi = find_first_zero_bit(port->msi_irq_in_use, MTK_MSI_IRQS_NUM);
|
|
|
+ if (msi < MTK_MSI_IRQS_NUM)
|
|
|
+ set_bit(msi, port->msi_irq_in_use);
|
|
|
+ else
|
|
|
+ return -ENOSPC;
|
|
|
+
|
|
|
+ return msi;
|
|
|
+}
|
|
|
+
|
|
|
+static void mtk_pcie_msi_free(struct mtk_pcie_port *port, unsigned long hwirq)
|
|
|
+{
|
|
|
+ clear_bit(hwirq, port->msi_irq_in_use);
|
|
|
+}
|
|
|
+
|
|
|
+static int mtk_pcie_msi_setup_irq(struct msi_controller *chip,
|
|
|
+ struct pci_dev *pdev, struct msi_desc *desc)
|
|
|
+{
|
|
|
+ struct mtk_pcie_port *port;
|
|
|
+ struct msi_msg msg;
|
|
|
+ unsigned int irq;
|
|
|
+ int hwirq;
|
|
|
+ phys_addr_t msg_addr;
|
|
|
+
|
|
|
+ port = mtk_pcie_find_port(pdev->bus, pdev->devfn);
|
|
|
+ if (!port)
|
|
|
+ return -EINVAL;
|
|
|
+
|
|
|
+ hwirq = mtk_pcie_msi_alloc(port);
|
|
|
+ if (hwirq < 0)
|
|
|
+ return hwirq;
|
|
|
+
|
|
|
+ irq = irq_create_mapping(port->msi_domain, hwirq);
|
|
|
+ if (!irq) {
|
|
|
+ mtk_pcie_msi_free(port, hwirq);
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
+
|
|
|
+ chip->dev = &pdev->dev;
|
|
|
+
|
|
|
+ irq_set_msi_desc(irq, desc);
|
|
|
+
|
|
|
+ /* MT2712/MT7622 only support 32-bit MSI addresses */
|
|
|
+ msg_addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
|
|
|
+ msg.address_hi = 0;
|
|
|
+ msg.address_lo = lower_32_bits(msg_addr);
|
|
|
+ msg.data = hwirq;
|
|
|
+
|
|
|
+ pci_write_msi_msg(irq, &msg);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static void mtk_msi_teardown_irq(struct msi_controller *chip, unsigned int irq)
|
|
|
+{
|
|
|
+ struct pci_dev *pdev = to_pci_dev(chip->dev);
|
|
|
+ struct irq_data *d = irq_get_irq_data(irq);
|
|
|
+ irq_hw_number_t hwirq = irqd_to_hwirq(d);
|
|
|
+ struct mtk_pcie_port *port;
|
|
|
+
|
|
|
+ port = mtk_pcie_find_port(pdev->bus, pdev->devfn);
|
|
|
+ if (!port)
|
|
|
+ return;
|
|
|
+
|
|
|
+ irq_dispose_mapping(irq);
|
|
|
+ mtk_pcie_msi_free(port, hwirq);
|
|
|
+}
|
|
|
+
|
|
|
+static struct msi_controller mtk_pcie_msi_chip = {
|
|
|
+ .setup_irq = mtk_pcie_msi_setup_irq,
|
|
|
+ .teardown_irq = mtk_msi_teardown_irq,
|
|
|
+};
|
|
|
+
|
|
|
+static struct irq_chip mtk_msi_irq_chip = {
|
|
|
+ .name = "MTK PCIe MSI",
|
|
|
+ .irq_enable = pci_msi_unmask_irq,
|
|
|
+ .irq_disable = pci_msi_mask_irq,
|
|
|
+ .irq_mask = pci_msi_mask_irq,
|
|
|
+ .irq_unmask = pci_msi_unmask_irq,
|
|
|
+};
|
|
|
+
|
|
|
+static int mtk_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
|
|
|
+ irq_hw_number_t hwirq)
|
|
|
+{
|
|
|
+ irq_set_chip_and_handler(irq, &mtk_msi_irq_chip, handle_simple_irq);
|
|
|
+ irq_set_chip_data(irq, domain->host_data);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static const struct irq_domain_ops msi_domain_ops = {
|
|
|
+ .map = mtk_pcie_msi_map,
|
|
|
+};
|
|
|
+
|
|
|
+static void mtk_pcie_enable_msi(struct mtk_pcie_port *port)
|
|
|
+{
|
|
|
+ u32 val;
|
|
|
+ phys_addr_t msg_addr;
|
|
|
+
|
|
|
+ msg_addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
|
|
|
+ val = lower_32_bits(msg_addr);
|
|
|
+ writel(val, port->base + PCIE_IMSI_ADDR);
|
|
|
+
|
|
|
+ val = readl(port->base + PCIE_INT_MASK);
|
|
|
+ val &= ~MSI_MASK;
|
|
|
+ writel(val, port->base + PCIE_INT_MASK);
|
|
|
+}
|
|
|
+
|
|
|
+static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
|
|
|
+ irq_hw_number_t hwirq)
|
|
|
+{
|
|
|
+ irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
|
|
|
+ irq_set_chip_data(irq, domain->host_data);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static const struct irq_domain_ops intx_domain_ops = {
|
|
|
+ .map = mtk_pcie_intx_map,
|
|
|
+};
|
|
|
+
|
|
|
+static int mtk_pcie_init_irq_domain(struct mtk_pcie_port *port,
|
|
|
+ struct device_node *node)
|
|
|
+{
|
|
|
+ struct device *dev = port->pcie->dev;
|
|
|
+ struct device_node *pcie_intc_node;
|
|
|
+
|
|
|
+ /* Setup INTx */
|
|
|
+ pcie_intc_node = of_get_next_child(node, NULL);
|
|
|
+ if (!pcie_intc_node) {
|
|
|
+ dev_err(dev, "no PCIe Intc node found\n");
|
|
|
+ return -ENODEV;
|
|
|
+ }
|
|
|
+
|
|
|
+ port->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
|
|
|
+ &intx_domain_ops, port);
|
|
|
+ if (!port->irq_domain) {
|
|
|
+ dev_err(dev, "failed to get INTx IRQ domain\n");
|
|
|
+ return -ENODEV;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (IS_ENABLED(CONFIG_PCI_MSI)) {
|
|
|
+ port->msi_domain = irq_domain_add_linear(node, MTK_MSI_IRQS_NUM,
|
|
|
+ &msi_domain_ops,
|
|
|
+ &mtk_pcie_msi_chip);
|
|
|
+ if (!port->msi_domain) {
|
|
|
+ dev_err(dev, "failed to create MSI IRQ domain\n");
|
|
|
+ return -ENODEV;
|
|
|
+ }
|
|
|
+ mtk_pcie_enable_msi(port);
|
|
|
+ }
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static irqreturn_t mtk_pcie_intr_handler(int irq, void *data)
|
|
|
+{
|
|
|
+ struct mtk_pcie_port *port = (struct mtk_pcie_port *)data;
|
|
|
+ unsigned long status;
|
|
|
+ u32 virq;
|
|
|
+ u32 bit = INTX_SHIFT;
|
|
|
+
|
|
|
+ while ((status = readl(port->base + PCIE_INT_STATUS)) & INTX_MASK) {
|
|
|
+ for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) {
|
|
|
+ /* Clear the INTx */
|
|
|
+ writel(1 << bit, port->base + PCIE_INT_STATUS);
|
|
|
+ virq = irq_find_mapping(port->irq_domain,
|
|
|
+ bit - INTX_SHIFT);
|
|
|
+ generic_handle_irq(virq);
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ if (IS_ENABLED(CONFIG_PCI_MSI)) {
|
|
|
+ while ((status = readl(port->base + PCIE_INT_STATUS)) & MSI_STATUS) {
|
|
|
+ unsigned long imsi_status;
|
|
|
+
|
|
|
+ while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) {
|
|
|
+ for_each_set_bit(bit, &imsi_status, MTK_MSI_IRQS_NUM) {
|
|
|
+ /* Clear the MSI */
|
|
|
+ writel(1 << bit, port->base + PCIE_IMSI_STATUS);
|
|
|
+ virq = irq_find_mapping(port->msi_domain, bit);
|
|
|
+ generic_handle_irq(virq);
|
|
|
+ }
|
|
|
+ }
|
|
|
+ /* Clear MSI interrupt status */
|
|
|
+ writel(MSI_STATUS, port->base + PCIE_INT_STATUS);
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ return IRQ_HANDLED;
|
|
|
+}
|
|
|
+
|
|
|
+static int mtk_pcie_setup_irq(struct mtk_pcie_port *port,
|
|
|
+ struct device_node *node)
|
|
|
+{
|
|
|
+ struct mtk_pcie *pcie = port->pcie;
|
|
|
+ struct device *dev = pcie->dev;
|
|
|
+ struct platform_device *pdev = to_platform_device(dev);
|
|
|
+ int err, irq;
|
|
|
+
|
|
|
+ irq = platform_get_irq(pdev, port->slot);
|
|
|
+ err = devm_request_irq(dev, irq, mtk_pcie_intr_handler,
|
|
|
+ IRQF_SHARED, "mtk-pcie", port);
|
|
|
+ if (err) {
|
|
|
+ dev_err(dev, "unable to request IRQ %d\n", irq);
|
|
|
+ return err;
|
|
|
+ }
|
|
|
+
|
|
|
+ err = mtk_pcie_init_irq_domain(port, node);
|
|
|
+ if (err) {
|
|
|
+ dev_err(dev, "failed to init PCIe IRQ domain\n");
|
|
|
+ return err;
|
|
|
+ }
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
static void __iomem *mtk_pcie_map_bus(struct pci_bus *bus,
|
|
|
unsigned int devfn, int where)
|
|
|
{
|
|
|
- struct pci_host_bridge *host = pci_find_host_bridge(bus);
|
|
|
- struct mtk_pcie *pcie = pci_host_bridge_priv(host);
|
|
|
+ struct mtk_pcie *pcie = bus->sysdata;
|
|
|
|
|
|
writel(PCIE_CONF_ADDR(where, PCI_FUNC(devfn), PCI_SLOT(devfn),
|
|
|
bus->number), pcie->base + PCIE_CFG_ADDR);
|
|
|
@@ -171,16 +675,34 @@ static struct pci_ops mtk_pcie_ops = {
|
|
|
.write = pci_generic_config_write,
|
|
|
};
|
|
|
|
|
|
-static void mtk_pcie_configure_rc(struct mtk_pcie_port *port)
|
|
|
+static int mtk_pcie_startup_port(struct mtk_pcie_port *port)
|
|
|
{
|
|
|
struct mtk_pcie *pcie = port->pcie;
|
|
|
- u32 func = PCI_FUNC(port->index << 3);
|
|
|
- u32 slot = PCI_SLOT(port->index << 3);
|
|
|
+ u32 func = PCI_FUNC(port->slot << 3);
|
|
|
+ u32 slot = PCI_SLOT(port->slot << 3);
|
|
|
u32 val;
|
|
|
+ int err;
|
|
|
+
|
|
|
+ /* assert port PERST_N */
|
|
|
+ val = readl(pcie->base + PCIE_SYS_CFG);
|
|
|
+ val |= PCIE_PORT_PERST(port->slot);
|
|
|
+ writel(val, pcie->base + PCIE_SYS_CFG);
|
|
|
+
|
|
|
+ /* de-assert port PERST_N */
|
|
|
+ val = readl(pcie->base + PCIE_SYS_CFG);
|
|
|
+ val &= ~PCIE_PORT_PERST(port->slot);
|
|
|
+ writel(val, pcie->base + PCIE_SYS_CFG);
|
|
|
+
|
|
|
+ /* 100ms timeout value should be enough for Gen1/2 training */
|
|
|
+ err = readl_poll_timeout(port->base + PCIE_LINK_STATUS, val,
|
|
|
+ !!(val & PCIE_PORT_LINKUP), 20,
|
|
|
+ 100 * USEC_PER_MSEC);
|
|
|
+ if (err)
|
|
|
+ return -ETIMEDOUT;
|
|
|
|
|
|
/* enable interrupt */
|
|
|
val = readl(pcie->base + PCIE_INT_ENABLE);
|
|
|
- val |= PCIE_PORT_INT_EN(port->index);
|
|
|
+ val |= PCIE_PORT_INT_EN(port->slot);
|
|
|
writel(val, pcie->base + PCIE_INT_ENABLE);
|
|
|
|
|
|
/* map to all DDR region. We need to set it before cfg operation. */
|
|
|
@@ -209,67 +731,94 @@ static void mtk_pcie_configure_rc(struct mtk_pcie_port *port)
|
|
|
writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0),
|
|
|
pcie->base + PCIE_CFG_ADDR);
|
|
|
writel(val, pcie->base + PCIE_CFG_DATA);
|
|
|
+
|
|
|
+ return 0;
|
|
|
}
|
|
|
|
|
|
-static void mtk_pcie_assert_ports(struct mtk_pcie_port *port)
|
|
|
+static void mtk_pcie_enable_port(struct mtk_pcie_port *port)
|
|
|
{
|
|
|
struct mtk_pcie *pcie = port->pcie;
|
|
|
- u32 val;
|
|
|
+ struct device *dev = pcie->dev;
|
|
|
+ int err;
|
|
|
|
|
|
- /* assert port PERST_N */
|
|
|
- val = readl(pcie->base + PCIE_SYS_CFG);
|
|
|
- val |= PCIE_PORT_PERST(port->index);
|
|
|
- writel(val, pcie->base + PCIE_SYS_CFG);
|
|
|
+ err = clk_prepare_enable(port->sys_ck);
|
|
|
+ if (err) {
|
|
|
+ dev_err(dev, "failed to enable sys_ck%d clock\n", port->slot);
|
|
|
+ goto err_sys_clk;
|
|
|
+ }
|
|
|
|
|
|
- /* de-assert port PERST_N */
|
|
|
- val = readl(pcie->base + PCIE_SYS_CFG);
|
|
|
- val &= ~PCIE_PORT_PERST(port->index);
|
|
|
- writel(val, pcie->base + PCIE_SYS_CFG);
|
|
|
+ err = clk_prepare_enable(port->ahb_ck);
|
|
|
+ if (err) {
|
|
|
+ dev_err(dev, "failed to enable ahb_ck%d\n", port->slot);
|
|
|
+ goto err_ahb_clk;
|
|
|
+ }
|
|
|
|
|
|
- /* PCIe v2.0 need at least 100ms delay to train from Gen1 to Gen2 */
|
|
|
- msleep(100);
|
|
|
-}
|
|
|
+ err = clk_prepare_enable(port->aux_ck);
|
|
|
+ if (err) {
|
|
|
+ dev_err(dev, "failed to enable aux_ck%d\n", port->slot);
|
|
|
+ goto err_aux_clk;
|
|
|
+ }
|
|
|
|
|
|
-static void mtk_pcie_enable_ports(struct mtk_pcie_port *port)
|
|
|
-{
|
|
|
- struct device *dev = port->pcie->dev;
|
|
|
- int err;
|
|
|
+ err = clk_prepare_enable(port->axi_ck);
|
|
|
+ if (err) {
|
|
|
+ dev_err(dev, "failed to enable axi_ck%d\n", port->slot);
|
|
|
+ goto err_axi_clk;
|
|
|
+ }
|
|
|
|
|
|
- err = clk_prepare_enable(port->sys_ck);
|
|
|
+ err = clk_prepare_enable(port->obff_ck);
|
|
|
if (err) {
|
|
|
- dev_err(dev, "failed to enable port%d clock\n", port->index);
|
|
|
- goto err_sys_clk;
|
|
|
+ dev_err(dev, "failed to enable obff_ck%d\n", port->slot);
|
|
|
+ goto err_obff_clk;
|
|
|
+ }
|
|
|
+
|
|
|
+ err = clk_prepare_enable(port->pipe_ck);
|
|
|
+ if (err) {
|
|
|
+ dev_err(dev, "failed to enable pipe_ck%d\n", port->slot);
|
|
|
+ goto err_pipe_clk;
|
|
|
}
|
|
|
|
|
|
reset_control_assert(port->reset);
|
|
|
reset_control_deassert(port->reset);
|
|
|
|
|
|
+ err = phy_init(port->phy);
|
|
|
+ if (err) {
|
|
|
+ dev_err(dev, "failed to initialize port%d phy\n", port->slot);
|
|
|
+ goto err_phy_init;
|
|
|
+ }
|
|
|
+
|
|
|
err = phy_power_on(port->phy);
|
|
|
if (err) {
|
|
|
- dev_err(dev, "failed to power on port%d phy\n", port->index);
|
|
|
+ dev_err(dev, "failed to power on port%d phy\n", port->slot);
|
|
|
goto err_phy_on;
|
|
|
}
|
|
|
|
|
|
- mtk_pcie_assert_ports(port);
|
|
|
-
|
|
|
- /* if link up, then setup root port configuration space */
|
|
|
- if (mtk_pcie_link_up(port)) {
|
|
|
- mtk_pcie_configure_rc(port);
|
|
|
+ if (!pcie->soc->startup(port))
|
|
|
return;
|
|
|
- }
|
|
|
|
|
|
- dev_info(dev, "Port%d link down\n", port->index);
|
|
|
+ dev_info(dev, "Port%d link down\n", port->slot);
|
|
|
|
|
|
phy_power_off(port->phy);
|
|
|
err_phy_on:
|
|
|
+ phy_exit(port->phy);
|
|
|
+err_phy_init:
|
|
|
+ clk_disable_unprepare(port->pipe_ck);
|
|
|
+err_pipe_clk:
|
|
|
+ clk_disable_unprepare(port->obff_ck);
|
|
|
+err_obff_clk:
|
|
|
+ clk_disable_unprepare(port->axi_ck);
|
|
|
+err_axi_clk:
|
|
|
+ clk_disable_unprepare(port->aux_ck);
|
|
|
+err_aux_clk:
|
|
|
+ clk_disable_unprepare(port->ahb_ck);
|
|
|
+err_ahb_clk:
|
|
|
clk_disable_unprepare(port->sys_ck);
|
|
|
err_sys_clk:
|
|
|
mtk_pcie_port_free(port);
|
|
|
}
|
|
|
|
|
|
-static int mtk_pcie_parse_ports(struct mtk_pcie *pcie,
|
|
|
- struct device_node *node,
|
|
|
- int index)
|
|
|
+static int mtk_pcie_parse_port(struct mtk_pcie *pcie,
|
|
|
+ struct device_node *node,
|
|
|
+ int slot)
|
|
|
{
|
|
|
struct mtk_pcie_port *port;
|
|
|
struct resource *regs;
|
|
|
@@ -288,34 +837,87 @@ static int mtk_pcie_parse_ports(struct mtk_pcie *pcie,
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|
|
return err;
|
|
|
}
|
|
|
|
|
|
- regs = platform_get_resource(pdev, IORESOURCE_MEM, index + 1);
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|
+ snprintf(name, sizeof(name), "port%d", slot);
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|
|
+ regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
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|
|
port->base = devm_ioremap_resource(dev, regs);
|
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|
if (IS_ERR(port->base)) {
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|
- dev_err(dev, "failed to map port%d base\n", index);
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|
+ dev_err(dev, "failed to map port%d base\n", slot);
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|
return PTR_ERR(port->base);
|
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|
}
|
|
|
|
|
|
- snprintf(name, sizeof(name), "sys_ck%d", index);
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|
+ snprintf(name, sizeof(name), "sys_ck%d", slot);
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|
port->sys_ck = devm_clk_get(dev, name);
|
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|
if (IS_ERR(port->sys_ck)) {
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|
- dev_err(dev, "failed to get port%d clock\n", index);
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|
|
+ dev_err(dev, "failed to get sys_ck%d clock\n", slot);
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|
|
return PTR_ERR(port->sys_ck);
|
|
|
}
|
|
|
|
|
|
- snprintf(name, sizeof(name), "pcie-rst%d", index);
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|
|
- port->reset = devm_reset_control_get_optional(dev, name);
|
|
|
+ /* sys_ck might be divided into the following parts in some chips */
|
|
|
+ snprintf(name, sizeof(name), "ahb_ck%d", slot);
|
|
|
+ port->ahb_ck = devm_clk_get(dev, name);
|
|
|
+ if (IS_ERR(port->ahb_ck)) {
|
|
|
+ if (PTR_ERR(port->ahb_ck) == -EPROBE_DEFER)
|
|
|
+ return -EPROBE_DEFER;
|
|
|
+
|
|
|
+ port->ahb_ck = NULL;
|
|
|
+ }
|
|
|
+
|
|
|
+ snprintf(name, sizeof(name), "axi_ck%d", slot);
|
|
|
+ port->axi_ck = devm_clk_get(dev, name);
|
|
|
+ if (IS_ERR(port->axi_ck)) {
|
|
|
+ if (PTR_ERR(port->axi_ck) == -EPROBE_DEFER)
|
|
|
+ return -EPROBE_DEFER;
|
|
|
+
|
|
|
+ port->axi_ck = NULL;
|
|
|
+ }
|
|
|
+
|
|
|
+ snprintf(name, sizeof(name), "aux_ck%d", slot);
|
|
|
+ port->aux_ck = devm_clk_get(dev, name);
|
|
|
+ if (IS_ERR(port->aux_ck)) {
|
|
|
+ if (PTR_ERR(port->aux_ck) == -EPROBE_DEFER)
|
|
|
+ return -EPROBE_DEFER;
|
|
|
+
|
|
|
+ port->aux_ck = NULL;
|
|
|
+ }
|
|
|
+
|
|
|
+ snprintf(name, sizeof(name), "obff_ck%d", slot);
|
|
|
+ port->obff_ck = devm_clk_get(dev, name);
|
|
|
+ if (IS_ERR(port->obff_ck)) {
|
|
|
+ if (PTR_ERR(port->obff_ck) == -EPROBE_DEFER)
|
|
|
+ return -EPROBE_DEFER;
|
|
|
+
|
|
|
+ port->obff_ck = NULL;
|
|
|
+ }
|
|
|
+
|
|
|
+ snprintf(name, sizeof(name), "pipe_ck%d", slot);
|
|
|
+ port->pipe_ck = devm_clk_get(dev, name);
|
|
|
+ if (IS_ERR(port->pipe_ck)) {
|
|
|
+ if (PTR_ERR(port->pipe_ck) == -EPROBE_DEFER)
|
|
|
+ return -EPROBE_DEFER;
|
|
|
+
|
|
|
+ port->pipe_ck = NULL;
|
|
|
+ }
|
|
|
+
|
|
|
+ snprintf(name, sizeof(name), "pcie-rst%d", slot);
|
|
|
+ port->reset = devm_reset_control_get_optional_exclusive(dev, name);
|
|
|
if (PTR_ERR(port->reset) == -EPROBE_DEFER)
|
|
|
return PTR_ERR(port->reset);
|
|
|
|
|
|
/* some platforms may use default PHY setting */
|
|
|
- snprintf(name, sizeof(name), "pcie-phy%d", index);
|
|
|
+ snprintf(name, sizeof(name), "pcie-phy%d", slot);
|
|
|
port->phy = devm_phy_optional_get(dev, name);
|
|
|
if (IS_ERR(port->phy))
|
|
|
return PTR_ERR(port->phy);
|
|
|
|
|
|
- port->index = index;
|
|
|
+ port->slot = slot;
|
|
|
port->pcie = pcie;
|
|
|
|
|
|
+ if (pcie->soc->setup_irq) {
|
|
|
+ err = pcie->soc->setup_irq(port, node);
|
|
|
+ if (err)
|
|
|
+ return err;
|
|
|
+ }
|
|
|
+
|
|
|
INIT_LIST_HEAD(&port->list);
|
|
|
list_add_tail(&port->list, &pcie->ports);
|
|
|
|
|
|
@@ -329,12 +931,14 @@ static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie)
|
|
|
struct resource *regs;
|
|
|
int err;
|
|
|
|
|
|
- /* get shared registers */
|
|
|
- regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
- pcie->base = devm_ioremap_resource(dev, regs);
|
|
|
- if (IS_ERR(pcie->base)) {
|
|
|
- dev_err(dev, "failed to map shared register\n");
|
|
|
- return PTR_ERR(pcie->base);
|
|
|
+ /* get shared registers, which are optional */
|
|
|
+ regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "subsys");
|
|
|
+ if (regs) {
|
|
|
+ pcie->base = devm_ioremap_resource(dev, regs);
|
|
|
+ if (IS_ERR(pcie->base)) {
|
|
|
+ dev_err(dev, "failed to map shared register\n");
|
|
|
+ return PTR_ERR(pcie->base);
|
|
|
+ }
|
|
|
}
|
|
|
|
|
|
pcie->free_ck = devm_clk_get(dev, "free_ck");
|
|
|
@@ -422,7 +1026,7 @@ static int mtk_pcie_setup(struct mtk_pcie *pcie)
|
|
|
}
|
|
|
|
|
|
for_each_available_child_of_node(node, child) {
|
|
|
- int index;
|
|
|
+ int slot;
|
|
|
|
|
|
err = of_pci_get_devfn(child);
|
|
|
if (err < 0) {
|
|
|
@@ -430,9 +1034,9 @@ static int mtk_pcie_setup(struct mtk_pcie *pcie)
|
|
|
return err;
|
|
|
}
|
|
|
|
|
|
- index = PCI_SLOT(err);
|
|
|
+ slot = PCI_SLOT(err);
|
|
|
|
|
|
- err = mtk_pcie_parse_ports(pcie, child, index);
|
|
|
+ err = mtk_pcie_parse_port(pcie, child, slot);
|
|
|
if (err)
|
|
|
return err;
|
|
|
}
|
|
|
@@ -443,7 +1047,7 @@ static int mtk_pcie_setup(struct mtk_pcie *pcie)
|
|
|
|
|
|
/* enable each port, and then check link status */
|
|
|
list_for_each_entry_safe(port, tmp, &pcie->ports, list)
|
|
|
- mtk_pcie_enable_ports(port);
|
|
|
+ mtk_pcie_enable_port(port);
|
|
|
|
|
|
/* power down PCIe subsys if slots are all empty (link down) */
|
|
|
if (list_empty(&pcie->ports))
|
|
|
@@ -480,9 +1084,12 @@ static int mtk_pcie_register_host(struct pci_host_bridge *host)
|
|
|
|
|
|
host->busnr = pcie->busn.start;
|
|
|
host->dev.parent = pcie->dev;
|
|
|
- host->ops = &mtk_pcie_ops;
|
|
|
+ host->ops = pcie->soc->ops;
|
|
|
host->map_irq = of_irq_parse_and_map_pci;
|
|
|
host->swizzle_irq = pci_common_swizzle;
|
|
|
+ host->sysdata = pcie;
|
|
|
+ if (IS_ENABLED(CONFIG_PCI_MSI) && pcie->soc->has_msi)
|
|
|
+ host->msi = &mtk_pcie_msi_chip;
|
|
|
|
|
|
err = pci_scan_root_bus_bridge(host);
|
|
|
if (err < 0)
|
|
|
@@ -513,6 +1120,7 @@ static int mtk_pcie_probe(struct platform_device *pdev)
|
|
|
pcie = pci_host_bridge_priv(host);
|
|
|
|
|
|
pcie->dev = dev;
|
|
|
+ pcie->soc = of_device_get_match_data(dev);
|
|
|
platform_set_drvdata(pdev, pcie);
|
|
|
INIT_LIST_HEAD(&pcie->ports);
|
|
|
|
|
|
@@ -537,9 +1145,23 @@ put_resources:
|
|
|
return err;
|
|
|
}
|
|
|
|
|
|
+static const struct mtk_pcie_soc mtk_pcie_soc_v1 = {
|
|
|
+ .ops = &mtk_pcie_ops,
|
|
|
+ .startup = mtk_pcie_startup_port,
|
|
|
+};
|
|
|
+
|
|
|
+static const struct mtk_pcie_soc mtk_pcie_soc_v2 = {
|
|
|
+ .has_msi = true,
|
|
|
+ .ops = &mtk_pcie_ops_v2,
|
|
|
+ .startup = mtk_pcie_startup_port_v2,
|
|
|
+ .setup_irq = mtk_pcie_setup_irq,
|
|
|
+};
|
|
|
+
|
|
|
static const struct of_device_id mtk_pcie_ids[] = {
|
|
|
- { .compatible = "mediatek,mt7623-pcie"},
|
|
|
- { .compatible = "mediatek,mt2701-pcie"},
|
|
|
+ { .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 },
|
|
|
+ { .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 },
|
|
|
+ { .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_v2 },
|
|
|
+ { .compatible = "mediatek,mt7622-pcie", .data = &mtk_pcie_soc_v2 },
|
|
|
{},
|
|
|
};
|
|
|
|
Bjorn Helgaas