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@@ -0,0 +1,35 @@
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+ARC PGU
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+
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+This is a display controller found on several development boards produced
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+by Synopsys. The ARC PGU is an RGB streamer that reads the data from a
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+framebuffer and sends it to a single digital encoder (usually HDMI).
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+
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+Required properties:
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+ - compatible: "snps,arcpgu"
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+ - reg: Physical base address and length of the controller's registers.
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+ - clocks: A list of phandle + clock-specifier pairs, one for each
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+ entry in 'clock-names'.
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+ - clock-names: A list of clock names. For ARC PGU it should contain:
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+ - "pxlclk" for the clock feeding the output PLL of the controller.
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+
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+Required sub-nodes:
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+ - port: The PGU connection to an encoder chip.
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+
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+Example:
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+
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+/ {
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+ ...
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+
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+ pgu@XXXXXXXX {
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+ compatible = "snps,arcpgu";
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+ reg = <0xXXXXXXXX 0x400>;
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+ clocks = <&clock_node>;
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+ clock-names = "pxlclk";
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+
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+ port {
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+ pgu_output: endpoint {
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+ remote-endpoint = <&hdmi_enc_input>;
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+ };
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+ };
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+ };
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+};
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