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@@ -123,9 +123,6 @@ struct bcm2835_desc {
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#define BCM2835_DMA_DATA_TYPE_S32 4
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#define BCM2835_DMA_DATA_TYPE_S32 4
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#define BCM2835_DMA_DATA_TYPE_S128 16
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#define BCM2835_DMA_DATA_TYPE_S128 16
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-#define BCM2835_DMA_BULK_MASK BIT(0)
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-#define BCM2835_DMA_FIQ_MASK (BIT(2) | BIT(3))
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-
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/* Valid only for channels 0 - 14, 15 has its own base address */
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/* Valid only for channels 0 - 14, 15 has its own base address */
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#define BCM2835_DMA_CHAN(n) ((n) << 8) /* Base address */
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#define BCM2835_DMA_CHAN(n) ((n) << 8) /* Base address */
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#define BCM2835_DMA_CHANIO(base, n) ((base) + BCM2835_DMA_CHAN(n))
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#define BCM2835_DMA_CHANIO(base, n) ((base) + BCM2835_DMA_CHAN(n))
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@@ -641,12 +638,6 @@ static int bcm2835_dma_probe(struct platform_device *pdev)
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goto err_no_dma;
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goto err_no_dma;
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}
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}
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- /*
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- * Do not use the FIQ and BULK channels,
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- * because they are used by the GPU.
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- */
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- chans_available &= ~(BCM2835_DMA_FIQ_MASK | BCM2835_DMA_BULK_MASK);
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-
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for (i = 0; i < pdev->num_resources; i++) {
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for (i = 0; i < pdev->num_resources; i++) {
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irq = platform_get_irq(pdev, i);
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irq = platform_get_irq(pdev, i);
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if (irq < 0)
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if (irq < 0)
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