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@@ -43,10 +43,33 @@ static unsigned int timer_clock_freq;
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#define TCSR_PWMA (1<<9)
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#define TCSR_ENALL (1<<10)
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+static unsigned int (*read_fn)(void __iomem *);
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+static void (*write_fn)(u32, void __iomem *);
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+
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+static void timer_write32(u32 val, void __iomem *addr)
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+{
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+ iowrite32(val, addr);
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+}
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+
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+static unsigned int timer_read32(void __iomem *addr)
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+{
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+ return ioread32(addr);
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+}
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+
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+static void timer_write32_be(u32 val, void __iomem *addr)
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+{
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+ iowrite32be(val, addr);
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+}
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+
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+static unsigned int timer_read32_be(void __iomem *addr)
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+{
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+ return ioread32be(addr);
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+}
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+
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static inline void xilinx_timer0_stop(void)
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{
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- out_be32(timer_baseaddr + TCSR0,
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- in_be32(timer_baseaddr + TCSR0) & ~TCSR_ENT);
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+ write_fn(read_fn(timer_baseaddr + TCSR0) & ~TCSR_ENT,
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+ timer_baseaddr + TCSR0);
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}
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static inline void xilinx_timer0_start_periodic(unsigned long load_val)
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@@ -54,10 +77,10 @@ static inline void xilinx_timer0_start_periodic(unsigned long load_val)
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if (!load_val)
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load_val = 1;
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/* loading value to timer reg */
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- out_be32(timer_baseaddr + TLR0, load_val);
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+ write_fn(load_val, timer_baseaddr + TLR0);
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/* load the initial value */
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- out_be32(timer_baseaddr + TCSR0, TCSR_LOAD);
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+ write_fn(TCSR_LOAD, timer_baseaddr + TCSR0);
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/* see timer data sheet for detail
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* !ENALL - don't enable 'em all
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@@ -72,8 +95,8 @@ static inline void xilinx_timer0_start_periodic(unsigned long load_val)
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* UDT - set the timer as down counter
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* !MDT0 - generate mode
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*/
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- out_be32(timer_baseaddr + TCSR0,
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- TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT);
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+ write_fn(TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT,
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+ timer_baseaddr + TCSR0);
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}
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static inline void xilinx_timer0_start_oneshot(unsigned long load_val)
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@@ -81,13 +104,13 @@ static inline void xilinx_timer0_start_oneshot(unsigned long load_val)
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if (!load_val)
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load_val = 1;
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/* loading value to timer reg */
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- out_be32(timer_baseaddr + TLR0, load_val);
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+ write_fn(load_val, timer_baseaddr + TLR0);
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/* load the initial value */
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- out_be32(timer_baseaddr + TCSR0, TCSR_LOAD);
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+ write_fn(TCSR_LOAD, timer_baseaddr + TCSR0);
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- out_be32(timer_baseaddr + TCSR0,
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- TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT);
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+ write_fn(TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT,
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+ timer_baseaddr + TCSR0);
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}
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static int xilinx_timer_set_next_event(unsigned long delta,
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@@ -133,7 +156,7 @@ static struct clock_event_device clockevent_xilinx_timer = {
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static inline void timer_ack(void)
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{
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- out_be32(timer_baseaddr + TCSR0, in_be32(timer_baseaddr + TCSR0));
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+ write_fn(read_fn(timer_baseaddr + TCSR0), timer_baseaddr + TCSR0);
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}
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static irqreturn_t timer_interrupt(int irq, void *dev_id)
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@@ -169,7 +192,7 @@ static __init void xilinx_clockevent_init(void)
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static u64 xilinx_clock_read(void)
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{
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- return in_be32(timer_baseaddr + TCR1);
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+ return read_fn(timer_baseaddr + TCR1);
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}
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static cycle_t xilinx_read(struct clocksource *cs)
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@@ -217,10 +240,10 @@ static int __init xilinx_clocksource_init(void)
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panic("failed to register clocksource");
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/* stop timer1 */
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- out_be32(timer_baseaddr + TCSR1,
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- in_be32(timer_baseaddr + TCSR1) & ~TCSR_ENT);
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+ write_fn(read_fn(timer_baseaddr + TCSR1) & ~TCSR_ENT,
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+ timer_baseaddr + TCSR1);
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/* start timer1 - up counting without interrupt */
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- out_be32(timer_baseaddr + TCSR1, TCSR_TINT|TCSR_ENT|TCSR_ARHT);
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+ write_fn(TCSR_TINT|TCSR_ENT|TCSR_ARHT, timer_baseaddr + TCSR1);
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/* register timecounter - for ftrace support */
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init_xilinx_timecounter();
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@@ -245,6 +268,15 @@ static void __init xilinx_timer_init(struct device_node *timer)
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BUG();
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}
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+ write_fn = timer_write32;
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+ read_fn = timer_read32;
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+
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+ write_fn(TCSR_MDT, timer_baseaddr + TCSR0);
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+ if (!(read_fn(timer_baseaddr + TCSR0) & TCSR_MDT)) {
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+ write_fn = timer_write32_be;
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+ read_fn = timer_read32_be;
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+ }
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+
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irq = irq_of_parse_and_map(timer, 0);
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of_property_read_u32(timer, "xlnx,one-timer-only", &timer_num);
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