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@@ -12,22 +12,109 @@
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/amba/bus.h>
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+#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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+#include <linux/irqchip.h>
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+#include <linux/irqchip/arm-gic.h>
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+#include <linux/mfd/dbx500-prcmu.h>
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+#include <linux/platform_data/arm-ux500-pm.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/of.h>
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+#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/perf/arm_pmu.h>
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#include <linux/regulator/machine.h>
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+#include <asm/outercache.h>
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+#include <asm/hardware/cache-l2x0.h>
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#include <asm/mach/map.h>
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+#include <asm/mach/arch.h>
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#include "setup.h"
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#include "board-mop500.h"
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#include "db8500-regs.h"
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+static int __init ux500_l2x0_unlock(void)
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+{
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+ int i;
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+ struct device_node *np;
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+ void __iomem *l2x0_base;
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+
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+ np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
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+ l2x0_base = of_iomap(np, 0);
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+ of_node_put(np);
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+ if (!l2x0_base)
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+ return -ENODEV;
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+
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+ /*
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+ * Unlock Data and Instruction Lock if locked. Ux500 U-Boot versions
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+ * apparently locks both caches before jumping to the kernel. The
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+ * l2x0 core will not touch the unlock registers if the l2x0 is
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+ * already enabled, so we do it right here instead. The PL310 has
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+ * 8 sets of registers, one per possible CPU.
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+ */
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+ for (i = 0; i < 8; i++) {
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+ writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
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+ i * L2X0_LOCKDOWN_STRIDE);
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+ writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +
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+ i * L2X0_LOCKDOWN_STRIDE);
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+ }
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+ iounmap(l2x0_base);
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+ return 0;
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+}
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+
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+static void ux500_l2c310_write_sec(unsigned long val, unsigned reg)
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+{
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+ /*
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+ * We can't write to secure registers as we are in non-secure
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+ * mode, until we have some SMI service available.
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+ */
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+}
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+
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+/*
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+ * FIXME: Should we set up the GPIO domain here?
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+ *
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+ * The problem is that we cannot put the interrupt resources into the platform
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+ * device until the irqdomain has been added. Right now, we set the GIC interrupt
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+ * domain from init_irq(), then load the gpio driver from
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+ * core_initcall(nmk_gpio_init) and add the platform devices from
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+ * arch_initcall(customize_machine).
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+ *
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+ * This feels fragile because it depends on the gpio device getting probed
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+ * _before_ any device uses the gpio interrupts.
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+*/
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+static void __init ux500_init_irq(void)
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+{
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+ struct device_node *np;
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+ struct resource r;
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+
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+ irqchip_init();
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+ np = of_find_compatible_node(NULL, NULL, "stericsson,db8500-prcmu");
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+ of_address_to_resource(np, 0, &r);
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+ of_node_put(np);
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+ if (!r.start) {
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+ pr_err("could not find PRCMU base resource\n");
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+ return;
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+ }
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+ prcmu_early_init(r.start, r.end-r.start);
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+ ux500_pm_init(r.start, r.end-r.start);
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+
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+ /* Unlock before init */
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+ ux500_l2x0_unlock();
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+ outer_cache.write_sec = ux500_l2c310_write_sec;
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+}
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+
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+static void ux500_restart(enum reboot_mode mode, const char *cmd)
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+{
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+ local_irq_disable();
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+ local_fiq_disable();
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+
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+ prcmu_system_reset(0);
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+}
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+
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/*
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* The PMU IRQ lines of two cores are wired together into a single interrupt.
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* Bounce the interrupt to the other core if it's not ours.
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Arnd Bergmann