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@@ -780,8 +780,6 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
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/* disable clock gating */
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vcn_v1_0_disable_clock_gating(adev);
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- vcn_v1_0_mc_resume_spg_mode(adev);
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-
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/* disable interupt */
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WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
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~UVD_MASTINT_EN__VCPU_EN_MASK);
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@@ -840,6 +838,8 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
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(0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
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(0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
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+ vcn_v1_0_mc_resume_spg_mode(adev);
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+
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/* take all subblocks out of reset, except VCPU */
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WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET,
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UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
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